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參數(shù)資料
| 型號： | S3041 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-48 8:1 Transmitter(帶片上高頻鎖相環(huán)的8選1 SONET/SDH傳送器（集成SONET OC-48接口器件）) |
| 中文描述： | TRANSMITTER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大小： | 195K |
| 代理商： | S3041 |
4
S3041
SONET/SDH/ATM OC-48 8:1 TRANSMITTER
January 7, 2000 / Revision G
S3041 ARCHITECTURE/FUNCTIONAL
DESIGN
Mux Operation
The S3041 performs the serializing stage in the pro-
cessing of a transmit SONET STS-48 bit serial data
stream. It converts the byte serial 311 Mbyte/sec data
stream to bit serial format at 2.488 Gbps. Diagnostic
loopback is provided (transmitter to receiver), and Line
Loopback is also provided (receiver to transmitter).
A high-frequency bit clock is generated from a
155.52 MHz frequency reference by using a fre-
quency synthesizer consisting of an on-chip
phase-locked loop circuit with a divider.
Clock Divider and Phase Detector
The Clock Divider and Phase Detector, shown in the
block diagram in Figure 2, contains monolithic PLL
components.
The REFCLK input must be generated from a differ-
ential LVPECL crystal oscillator which has a
frequency accuracy of better than 20 ppm in order
for the VCOCLK frequency to have the same accu-
racy required for operation in a SONET system.
In order to meet the .01 UI SONET jitter specifica-
tions, the maximum reference clock jitter must be
guaranteed over the 12 KHz to 20 MHz bandwidth.
For details of reference clock jitter requirements, see
Table 2.
Timing Generator
The Timing Generator function, seen in Figure 2, pro-
vides two separate functions. It provides a byte rate
version of the TSCLK, and a mechanism for aligning
the phase between the incoming byte clock and the
clock which loads the parallel-to-serial shift register.
The PCLK output is a byte rate version of TSCLK.
For STS-48, the PCLK frequency is 311 MHz. PCLK
is intended for use as a byte speed clock for up-
stream multiplexing and overhead processing circuits.
Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S3041 device.
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK byte clock
timing domain to the internally generated byte clock
timing domain, which is phase aligned to TSCLK.
The Timing Generator also produces a feedback ref-
erence clock to the Phase Detector. A counter divides
the synthesized clock down to the same frequency
as the reference clock REFCLK.
Parallel-to-Serial Converter
The FIFO is used to accomodate phase differences
between the internal byte clock and the external
PICLK. The READ and PULSE signals are used to
control the FIFO to prevent overflow/underflow con-
ditions.
The Parallel-to-Serial converter shown in Figure 2 is
comprised of a FIFO and a parallel-to-serial register.
The FIFO latches the data from the PIN[7:0] bus on
the rising edge of PICLK. The parallel-to-serial regis-
ter is a parallel loadable shift register which takes its
parallel input from the FIFO.
An internally generated byte clock, which is phase
aligned to the transmit serial clock as described in the
Timing Generator description, activates the parallel
data transfer between registers. The serial data is
shifted out of the second register at the TSCLK rate
.
Table 2. Reference Jitter Limits
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| S304100 | 制造商:Microsemi Corporation 功能描述:1KV 40A 2PIN DO-5 - Bulk |
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