- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365399 > S29NS128N0SBJW002 (SPANSION LLC) Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory PDF資料下載
參數(shù)資料
| 型號： | S29NS128N0SBJW002 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 9.20 X 8 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 14/86頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | S29NS128N0SBJW002 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
12
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
6.
Input/Output Descriptions
A23–A16
=
Address Inputs, S29NS256N
A22–A16
=
Address Inputs, S29NS128N
A21-A16
= Address Inputs, S29NS064N
A/DQ15–A/DQ0
=
Multiplexed Address/Data input/output
CE#
=
Chip Enable Input. Asynchronous relative to CLK for the Burst mode
OE#
=
Output Enable Input. Asynchronous relative to CLK for the Burst mode
WE#
=
Write Enable Input
V
CC
V
CCQ
V
SS
V
SSQ
NC
=
Device Power Supply (1.70V–1.95V)
=
Input/Output Power Supply (1.70V–1.95V)
=
Ground
=
Input/Output Ground
=
No Connect; not connected internally
RDY
=
Ready output; indicates the status of the Burst read. V
OL
= data invalid.
V
OH
= data valid
The first rising edge of CLK in conjunction with AVD# low latches address input and
activates burst mode operation. After the initial word is output, subsequent rising edges
of CLK increment the internal address counter. CLK should remain low during
asynchronous access
CLK
=
AVD#
=
Address Valid input. Indicates to device that the valid address is present on the
address inputs (address bits A15–A0 are multiplexed, address bits Amax–A16 are
address only)
V
IL
= for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched on rising edge of CLK.
V
IH
= device ignores address inputs
Hardware reset input. V
IL
= device resets and returns to reading array data
Hardware write protect input. V
IL
= disables writes to SA257–258 (S29NS256N),
SA129–130 (S29NS128N) or SA129-130 (S29NS064N). Should be at V
IH
for all other
conditions
RESET#
=
WP#
=
ACC
=
At 9V, accelerates programming; automatically places device in unlock bypass mode.
At V
IL
, disables program and erase functions. Should be at V
IH
for all other conditions
6.1
Logic Symbol
5 to
8
A/DQ15–
A/DQ0
A
m
a
x
- A16
CE#
OE#
WE#
RE
S
ET#
CLK
RDY
AVD#
WP#
ACC
A
m
a
x
indic
a
te
s
the highe
s
t order
a
ddre
ss
b
it.
16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29NS128N0SBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS256N0PBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS256N0PBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS256N0PBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS256N0SBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS128N0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128P | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128P0PBJW000 | 功能描述:閃存 128M (8MX16) 66MHz Simultaneous R/W RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S29NS128P0PBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29NS128P0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。