參數(shù)資料
型號： S29NS064N0PBJW002
廠商： SPANSION LLC
元件分類： DRAM
英文描述： Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 7.70 X 6.20 MM, LEAD FREE, FBGA-44
文件頁數(shù)： 20/86頁
文件大小： 1036K
代理商： S29NS064N0PBJW002
18
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
8.7
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing in one of the
other banks of memory. An erase operation may also be suspended to read from or program to another
location within the same bank (except the sector being erased).
Figure 19.13 on page 75
shows how read
and write cycles may be initiated for simultaneous operation with zero latency. Refer to the table
DC
Characteristics
on page 62
for read-while-program and read-while-erase current specifications.
8.8
Writing Commands/Command Sequences
The device has inputs/outputs that accept both address and data information. To write a command or
command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to V
IL
, and OE# to V
IH
when providing an address to the device, and drive
WE# and CE# to V
IL
, and OE# to V
IH
. when writing commands or data.
The device features an
Unlock Bypass
mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 14-17 indicates the
address space that each sector occupies. The device address space is divided into multiple banks. A “bank
address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address
bits required to uniquely select a sector.
Refer to the DC Characteristics table for write mode current specifications. The section
AC Characteristics
on page 64
contains timing specification tables and timing diagrams for write operations.
8.9
Accelerated Program and Erase Operations
The device offers accelerated program and erase operation through the ACC function. ACC is primarily
intended to allow faster manufacturing throughput at the factory and not to be used in system operations.
If the system asserts V
HH
on this input, the device automatically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the input to reduce the time required for program and erase operations.
The system can then use the abbreviated Embedded Programming command and Write Buffer Load
command sequence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is
required while in Unlock Bypass mode, the
full 3-cycle RESET command sequence must be used to reset
the device
. Removing V
HH
from the ACC input, upon completion of the embedded program or erase
operation, returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to
V
HH
.
Note that the ACC pin must not be at V
HH
for operations other than accelerated programming, or device
damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of
the device may result
.
When at V
IL
, ACC locks all sectors. ACC should be at V
IH
for all other conditions.
8.10
Write Buffer Programming Operation
Write Buffer Programming
allows the system to write a maximum of
32
words in one programming
operation. This results in a faster effective word programming time than the standard “word” programming
algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address
in which programming will occur. At this point, the system writes the number of “
word locations minus 1
”
that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the
device how many write buffer addresses will be loaded with data and therefore when to expect the “Program
Buffer to Flash” confirm command. The number of locations to program cannot exceed the size of the write
buffer or the operation will abort. (NOTE: The number loaded = the number of locations to program minus 1.
For example, if the system will program 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first address/data
pair to be programmed, and selects the “write-buffer-page” address. All subsequent address/data pairs
must
fall within the “selected-write-buffer-page”, and be loaded in sequential order.
The “write-buffer-page” is selected by using the addresses A
MAX
-A5 where A
MAX
is A23 for S29NS256N, A22
for S29NS128N and A21 for S29NS064N.
相關PDF資料
PDF描述
S29NS064N0PBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW000 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW000 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
相關代理商/技術參數(shù)
參數(shù)描述
S29NS064N0PBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128J0LBAW00 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
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