參數(shù)資料
型號(hào): S29GL128N11FFIV10
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology
中文描述: 8M X 16 FLASH 3V PROM, 110 ns, PBGA64
封裝: 13 X 11 MM, LEAD FREE, FBGA-64
文件頁(yè)數(shù): 94/100頁(yè)
文件大小: 952K
代理商: S29GL128N11FFIV10
92
S29GL-N MirrorBit Flash Family
S29GL-N_00_B3 October 13, 2006
D a t a S h e e t
Revision Summary
Revision A (September 2, 2003)
Initial Release.
Revision A1 (October 16, 2003)
Global
Added LAA064 package.
Distinctive Characteristics, Performance Characteristics
Clarified fifth bullet information.
Added RTSOP to Package Options.
Distinctive Characteristics, Softw are and Hardw are Features
Clarified
Password Sector Protection
to
Advanced Sector Protection
Connection Diagrams
Removed Note.
Ordering I nformation
Modified Package codes
Device Bus Operations, Table 1
Modified Table, removed Note.
Sector Address Tables
All address ranges doubled in all sector address tables.
Sector Protection
Lock Register: Corrected text to reflect 3 bits instead of 4.
Table 6, Lock Register: Corrected address range from DQ15-5 to DQ15-3; removed DQ4 and
DQ3; Corrected DQ15-3 Lock Register to Don’t Care.
Table 7, Sector Protection Schemes: Corrected Sector States.
Command Definitions
Table 12, Command Definitions, x16
Nonvolatile Sector Protection Command Set Entry Second Cycle Address corrected from 55
to 2AA.
Legend: Clarified PWDx, DATA
Notes: Clarified Note 19.
Table 13, Command Definitions, x8
Password Read and Unlock Addresses and Data corrected.
Legend: Clarified PWDx, DATA
Notes: Clarified Note 19.
Test Conditions
Table 17 on page 75
, Test Specifications and
Figure 10, on page 76
, Input Waveforms and
Measurement Levels: Corrected Input Pulse Levels to 0.0–VIO; corrected Input timing mea-
surement reference levels to 0.5V
IO
.
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