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參數(shù)資料
| 型號： | S29GL128N11FAIVH0 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 110 ns, PBGA64 |
| 封裝： | 10 X 13 MM, 1 MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 38/74頁 |
| 文件大?。?/td> | 1593K |
| 代理商： | S29GL128N11FAIVH0 |
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May 1, 2006 S29GL-N_01_A0
S29GL-N
41
Data
She e t
10.8
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed
by the address of the sector to be erased, and the sector erase command. Table 11.1 on page 46 and
Table 11.3 on page 48 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and
command following the exceeded time-out may or may not be accepted. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress.
The system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase
Timer on page 55.). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to Write Operation Status on page 50 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,
the sector erase command sequence should be reinitiated once the device has returned to reading array
data, to ensure data integrity.
Figure 10.4 on page 41 illustrates the algorithm for the erase operation. Refer to Erase and Program
Operations on page 62 for parameters, and Figure 18.6 on page 64 for timing diagrams.
Figure 10.4 Erase Operation
Notes
1. See Table 11.1 on page 46 and Table 11.3 on page 48 for program command sequence.
2. See DQ3: Sector Erase Timer on page 55 for information on the sector erase timer.
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
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