參數(shù)資料
型號(hào)： S29GL032M10TAIR42
廠商： SPANSION LLC
元件分類： PROM
英文描述： CAP .1UF 1000V CER 10% X7R RADL
中文描述： 2M X 16 FLASH 3V PROM, 100 ns, PDSO48
封裝： MO-142-EC, TSOP-48
文件頁數(shù)： 82/160頁
文件大小： 4727K
代理商： S29GL032M10TAIR42
28
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00A5 April 30, 2004
Pr e l i m i n a r y
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector Group Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors
are protected (for boot sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors will be
protected or unprotected as determined by the method described in “Sector Group Protection and Unprotection”.
All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending
on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Operation
CE#
OE#
WE
#
RESET#
WP#
ACC
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
LL
H
X
AIN
DOUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
LH
L
H
(Note
3)
XAIN
(Note
4)
(Note
4)
Accelerated Program
LH
L
H
(Note
3)
VHH
AIN
(Note
4)
(Note
4)
Standby
VCC
± 0.3
V
XX
VCC ±
0.3 V
X
H
X
High-Z High-Z
High-Z
Output Disable
L
H
X
High-Z High-Z
High-Z
Reset
X
L
X
High-Z High-Z
High-Z
Sector Group Protect
(Note 2)
LH
L
VID
HX
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L
(Note
4)
XX
Sector Group
Unprotect
(Note 2)
LH
L
VID
HX
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L
(Note
4)
XX
Temporary Sector
Group Unprotect
XX
X
VID
HX
AIN
(Note
4)
(Note
4)
High-Z
相關(guān)PDF資料
PDF描述
S29GL032M11TCIR42 2M X 16 FLASH 3V PROM, 110 ns, PDSO48
S29GL064A10BAIW12 4M X 16 FLASH 3V PROM, 100 ns, PBGA64
S29GL128N11FAIVH0 16M X 16 FLASH 3V PROM, 110 ns, PBGA64
S29GL128N11FFIVH2 16M X 16 FLASH 3V PROM, 110 ns, PBGA64
S29JL032J70TFI213 2M X 16 FLASH 3V PROM, 70 ns, PDSO48
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