參數(shù)資料
型號: S29GL032M10BAIR02
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology
中文描述: 4M X 8 FLASH 3V PROM, 100 ns, PBGA48
封裝: 8 X 9 MM, FBGA-48
文件頁數(shù): 82/116頁
文件大小: 1656K
代理商: S29GL032M10BAIR02
80
S29GL-M MirrorBit
TM
Flash Family
S29GL-M_00_B6 October 10, 2006
D a t a S h e e t
AC Characteristics
Read-Only Operations—S29GL256M Only
Notes:
1.
2.
Not 100% tested.
See
Figure 11
and
Table 37
for test specifications.
Read-Only Operations—S29GL128M only
Notes:
1.
2.
Not 100% tested.
See
Figure 11
and
Table 37
for test specifications.
Parameter
Description
Test Setup
Speed Options
Unit
J EDEC
Std.
10
11
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
100
100
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
100
100
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
100
100
ns
t
PACC
Page Access Time
Max
30
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Parameter
Description
Test Setup
Speed Options
Unit
J EDEC
Std.
90
10
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
90
100
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
90
100
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
90
100
ns
t
PACC
Page Access Time
Max
25
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
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