參數(shù)資料
型號： S29CL032J0PFAM020
廠商： SPANSION LLC
元件分類： PROM
英文描述： 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80
文件頁數(shù)： 17/79頁
文件大?。?/td> 2994K
代理商： S29CL032J0PFAM020
24
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B3 March 30, 2009
Da ta
Sh e e t
banks was in the middle of either a program or erase operation when RESET# was asserted, the user must
wait a period of tREADY before accessing that bank.
Asserting RESET# during a program or erase operation leaves erroneous data stored in the address
locations being operated on at the time of device reset. These locations need updating after the reset
operation is complete. See Section 18.4 for timing specifications.
Asserting RESET# active during VCC and VIO power-up is required to guarantee proper device initialization
until VCC and VIO have reached their steady state voltages. See Section 18.1.
8.4
Synchronous (Burst) Read Mode & Configuration Register
When a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode
can be used to significantly reduce the overall time needed for the device to output array data. After an initial
access time required for the data from the first address location, subsequent data is output synchronized to a
clock input provided by the system.
The device offers a linear method of burst read operation which is discussed in Section 8.4.1, 2-, 4-, 8-
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration
register must be set in order to enable the burst read mode. Other Configuration Register settings include the
number of wait states to insert before the initial word (tIACC) of each burst access and when RDY indicates
that data is ready to be read. Prior to entering the burst mode, the system first determines the configuration
register settings (and read the current register settings if desired via the Read Configuration Register
command sequence), then write the configuration register command sequence. See Section 8.4.3,
on page 73 for further details. Once the configuration register is written to enable burst mode operation, all
subsequent reads from the array are returned using the burst mode protocols.
Figure 8.2 Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
tIACC specification: The time from the rising edge of the first clock cycle after addresses are latched to valid
data on the device outputs.
Configuration register setting CR13-CR10: The total number of clock cycles (wait states) that occur before
valid data appears on the device outputs. The effect is that tIACC is lengthened.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(D15 = 1)
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