參數(shù)資料
型號(hào)： S29CD016J1MQFM133
廠商： SPANSION LLC
元件分類： PROM
英文描述： 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
中文描述： 512K X 32 FLASH 2.7V PROM, 54 ns, PQFP80
封裝： LEAD FREE, PLASTIC, MO-108CB-1, QFP-80
文件頁(yè)數(shù)： 26/76頁(yè)
文件大小： 1245K
代理商： S29CD016J1MQFM133
24
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
D a t a
S h e e t
( P r e l i m i n a r y )
Figure 8.4
Initial Burst Delay Control
Notes
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or five clock cycles
8.4.3
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon power-up
or hardware reset, the device defaults to the asynchronous read mode and the configuration register settings
are in their default state. (See
Table 8.6
for the default Configuration Register settings.) The host system
determines the proper settings for the entire configuration register, and then execute the Set Configuration
Register command sequence before attempting burst operations. The configuration register is not reset after
deasserting CE#.
The Configuration Register does not occupy any addressable memory location, but rather, is accessed by the
Configuration Register commands. The Configuration Register is readable at any time, however, writing the
Configuration Register is restricted to times when the Embedded Algorithm is not active. If the user
attempts to write the Configuration Register while the Embedded Algorithm is active, the write operation is
ignored and the contents of the Configuration Register remain unchanged.
The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read operation,
DQ31–DQ16 returns all zeroes. Also, the Configuration Register reads operate the same as the Autoselect
command reads. When the command is issued, the bank address is latched along with the command. Read
operations to the bank that was specified during the Configuration Register read command return
Configuration Register contents. Read operations to the other bank return flash memory data. Either bank
address is permitted when writing the Configuration Register read command.
The configuration register can be read with a four-cycle command sequence. See
Section 20.1,
Command
Definitions
on page 69
for sequence details.
Table 8.5
describes the Configuration Register settings.
CLK
ADV#
Addre
ss
e
s
DQ
3
1-DQ0
3
DQ
3
1-DQ0
4
DQ
3
1-DQ0
5
V
a
lid Addre
ss
Three CLK Del
a
y
2nd CLK
3
rd CLK
4th CLK
5th CLK
1
s
t CLK
Fo
u
r CLK Del
a
y
Addre
ss
1 L
a
tched
Five CLK Del
a
y
D0
D1
D2
D
3
D0
D1
D2
D0
D1
D2
D
3
D4
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