參數(shù)資料
型號: S29CD016J1MQFM002
廠商: Spansion Inc.
英文描述: 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
中文描述: 32/16兆位的CMOS 2.6伏或3.3伏,只有同時讀/寫,雙啟動,突發(fā)模式閃存記憶體與VersatileI /輸出
文件頁數(shù): 28/76頁
文件大?。?/td> 1245K
代理商: S29CD016J1MQFM002
26
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
D a t a
S h e e t
( P r e l i m i n a r y )
address must appear on the appropriate highest order address bits.
Table 8.7
shows the remaining address
bits that are don’t care. When all necessary bits have been set as required, the programming equipment may
then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command. This method does not require VID. See
Section 20.1,
Command Definitions
on page 69
for details
on using the autoselect mode. Autoselect mode can be used in either synchronous (Burst) mode or
asynchronous (Non Burst) mode.
The system must write the reset command to exit the autoselect mode and return to reading the array data.
See
Table 8.7
for command sequence details.
Legend
L = Logic Low = V
IL
, H = Logic High = V
IH
, SA = Sector Address, X = Don’t care.
Note
The autoselect codes can also be accessed in-system via command sequences. See
Table 20.2
.
8.6
VersatileI/O (V
IO
) Control
The VersatileI/O (V
IO
) control allows the host system to set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the V
IO
pin. The output voltage generated on the device is determined based on the V
IO
(V
CCQ
) level. For the 2.6 V
(CD-J), a V
IO
of 1.65 V–3.6 V (CD032J has a V
IO
of 1.65 V to 2.75 V) allows the device to interface with I/Os
lower than 2.5 V. For a 3.3 V V
CC
(CL-J), a V
IO
of 1.65 V–3.60 V allows the device to interface with I/Os lower
than 3.0 V.
8.7
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in
detail in the following sections. However, prior to any programming and or erase operation, devices must be
set up appropriately as outlined in the configuration register (
Table 8.5 on page 25
). During a synchronous
write operation, to write a command or command sequence (including programming data to the device and
erasing sectors of memory), the system must drive AVD# and CE# to V
IL
, and OE# to V
IH
when providing an
address to the device, and drive WE# and CE# to V
IL
, and OE# to V
IH
when writing commands or
programming data.
8.7.1
Programming
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program setup command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically generates the program pulses and verifies the programmed cell
Table 8.7
S29CD-J & S29CL-J Flash Family Autoselect Codes (High Voltage Method)
Description
CE#
OE#
WE#
A19
to
A11
A10
A9
A8
A7
A6
A5
to
A4
A3
A2
A1
A0
DQ7
to DQ0
Manufacturer ID
:
Spansion
L
L
H
X
X
V
ID
X
X
L
X
X
X
L
L
0001h
A
Read Cycle 1
L
L
H
X
X
V
ID
X
L
L
X
L
L
L
H
007Eh
Read Cycle 2
L
L
H
X
X
V
ID
X
L
L
L
H
H
H
L
08h or 36h for CD016J
46h for CL016J
09h for CD032J
49h for CL032J
Read Cycle 3
L
L
H
X
X
V
ID
X
L
L
L
H
H
H
H
0000h
Top Boot Option
0001h
Bottom Boot Option
PPB Protection Status
L
L
H
SA
X
V
ID
X
L
L
L
L
L
H
L
0000h (unprotected)
0001h (protected)
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