參數(shù)資料
型號(hào)： S29CD016J1MQFI103
廠商： Spansion Inc.
英文描述： 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
中文描述： 32/16兆位的CMOS 2.6伏或3.3伏，只有同時(shí)讀/寫，雙啟動(dòng)，突發(fā)模式閃存記憶體與VersatileI /輸出
文件頁數(shù)： 56/76頁
文件大?。?/td> 1245K
代理商： S29CD016J1MQFI103
54
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
D a t a
S h e e t
( P r e l i m i n a r y )
18.3
Synchronous Operations
Notes
1.
2. Not 100% tested
3. Recommended 50% Duty Cycle
Using the max t
AAVS
and min t
ADVCS
specs together will result in incorrect data output.
Table 18.3
Burst Mode Read for 32 Mb and 16 Mb
Parameter
Description
Speed Options
Unit
JEDEC
Std.
75MHz,
OR
66MHz,
OP
56MHz,
OM
40MHz,
OJ
t
BACC
t
ADVCS
t
ADVCH
t
ADVP
t
BDH
Burst Access Time Valid Clock to Output Delay
Max
7.5 FBGA
8
8
8
ns
ADV# Setup Time to Rising Edge of CLK
Min
6
6
6
6
ns
ADV# Hold Time from Rising Edge of CLK
Min
1.5
ns
ADV# Pulse Width
Min
7.5
8.5
9.5
10.5
ns
Valid Data Hold from CLK
(Note 2)
Min
2
2
3
3
ns
t
INDS
CLK to Valid IND/WAIT#
(Note 2)
Max
7.5 FBGA
9 FBGA
9.5 PQFP
10 FBGA
10 PQFP
17
ns
t
INDH
IND/WAIT# Hold from CLK
(Note 2)
Min
2
2
3
3
ns
t
IACC
ADV or ADD Valid (Whichever Occurs Last) to Valid
Data Out, Initial Burst Access
Max
48
54
54
54
ns
t
CLK
CLK Period
Min
13.3
15.15
17.85
25
ns
Max
60
t
CR
t
CF
t
CLKH
t
CLKL
t
OE
CLK Rise Time
(Note 2)
Max
3
ns
CLK Fall Time
(Note 2)
Max
3
ns
CLK High Time
(Note 3)
Min
6.65
6.8
8.0
11.25
ns
CLK Low Time
(Note 3)
Min
6.65
27
27
27
ns
Output Enable to Output Valid
Max
20
20
ns
t
DF
t
OEZ
Output Enable to Output High Z
(Note 2)
Min
2
2
3
3
ns
Max
7.5
10
15
17
t
EHQZ
t
CEZ
t
CES
t
AAVS
t
AAVH
t
RSTZ
t
WADVH1
t
WADVH2
Chip Enable to Output High Z
(Note 2)
Max
7.5
10
15
17
ns
CE# Setup Time to Clock
Min
4
4
5
6
ns
ADV# Falling Edge to Address Valid
(Note 1)
Max
6.5
6.5
6.5
6.5
ns
Address Hold Time from Rising Edge of AVD#
Min
15
15
15
15
ns
RESET# Low to Output High Z
(Note 2)
Max
7.5
10
15
17
ns
ADV# Falling Edge to WE# Falling Edge
Min
5
5
5
5
ns
ADV# Rising Edge to WE# Rising Edge
Min
10
10
10
10
ns
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