參數(shù)資料
型號(hào)： S29CD016J1MFFM002
廠商： Spansion Inc.
英文描述： 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
中文描述： 32/16兆位的CMOS 2.6伏或3.3伏，只有同時(shí)讀/寫(xiě)，雙啟動(dòng)，突發(fā)模式閃存記憶體與VersatileI /輸出
文件頁(yè)數(shù)： 24/76頁(yè)
文件大?。?/td> 1245K
代理商： S29CD016J1MFFM002
22
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
D a t a
S h e e t
( P r e l i m i n a r y )
Like the main memory access, the Secured Silicon Sector memory is accessed with the same burst or
asynchronous timing as defined in the Configuration Register. However, the user must recognize burst
operations past the 256 byte Secured Silicon boundary returns invalid data.
Burst read operations occur only to the main flash memory arrays. The Configuration Register and protection
bits are treated as single cycle reads, even when burst mode is enabled. Read operations to these locations
results in the data remaining valid while OE# is at V
IL
, regardless of the number of CLK cycles applied to the
device.
8.4.1
2-, 4-, 8- Double Word Linear Burst Operation
In a linear burst read operation, a fixed number of words (2, 4, or 8 double words) are read from consecutive
addresses that are determined by the group within which the starting address falls. Note that 1 double word =
32 bits. See
Table 8.2
for all valid burst output sequences.
The IND/WAIT# signal, or End of Burst Indicator signal, transitions active (V
IL
) during the last transfer of data
in a linear burst read before a wrap around. This transition indicates that the system should initiate another
ADV# to start the next burst access. If the system continues to clock the device, the next access wraps
around to the starting address of the previous burst access. The IND/WAIT# signal is floating when not active.
Notes
1. The default configuration in the Control Register for Bit 6 is “1,” indicating that the device delivers data on the rising edge of the CLK
signal.
2. The device is capable of holding data for one CLK cycle.
3. If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to
asynchronous read mode. When this happens, the DQ data bus signal floats and the Configuration Register contents are reset to their
default conditions.
4. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken to V
IH
at any time during the burst linear or
burst cycle, the device immediately exits the burst sequence and floats the DQ bus signal.
5. Restarting a burst cycle is accomplished by taking CE# and ADV# to V
IL
.
6. A burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge,
whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the previous address is discarded and
subsequent burst transfers are invalid. A new burst is initiated when ADV# transitions back to V
IH
before a clock edge.
7. The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-asserting the OE# pin to V
IH
during a
burst operation floats the data bus, but the device continues to operate internally as if the burst sequence continues until the linear burst
is complete. The OE# pin does not halt the burst sequence, The DQ bus remains in the float state until OE# is taken to V
IL
.
8. Halting the burst sequence is accomplished by either taking CE# to V
IH
or re-issuing a new ADV# pulse.
The IND/WAIT# signal is controlled by the OE# signal. If OE# is at V
IH
, the IND/WAIT# signal floats and is not
driven. If OE# is at V
IL
, the IND/ WAIT# signal is driven at V
IH
until it transitions to V
IL
, indicating the end of
the burst sequence.
Table 8.3
lists the valid combinations of the Configuration Register bits that impact the
IND/WAIT# timing. See
Figure 8.3
for the IND/WAIT# timing diagram.
Table 8.2
32- Bit Linear and Burst Data Order
Data Transfer Sequence
(Independent of the WORD# pin)
Output Data Sequence
(Initial Access Address, x16)
Two Linear Data Transfers
0-1 (A0 = 0)
1-0 (A0 = 1)
Four Linear Data Transfers
0-1-2-3 (A0:A-1/A1-A0 = 00)
1-2-3-0 (A0:A-1/A1-A0 = 01)
2-3-0-1 (A:A-1/A1-A0 = 10)
3-0-1-2 (A0:A-1/A1-A0 = 11)
Eight Linear Data Transfers
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
相關(guān)PDF資料
PDF描述
S29CD016J1MFFM003 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MFFM033 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MFFM100 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MFFM102 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MFFM103 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29CD016J1MFFM003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MFFM033 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MFFM100 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MFFM102 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
S29CD016J1MFFM103 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*