參數(shù)資料
型號(hào)： S29CD016G0MFAN003
廠商： SPANSION LLC
元件分類： PROM
英文描述： 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 512K X 32 FLASH 2.7V PROM, 64 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80
文件頁數(shù)： 39/81頁
文件大?。?/td> 1276K
代理商： S29CD016G0MFAN003
42
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
15.6
Accelerated Program Command
The Accelerated Chip Program mode is designed to improve the Word or Double Word programming speed.
Improving the programming speed is accomplished by using the ACC pin to supply both the wordline voltage
and the bitline current instead of using the VPP pump and drain pump, which is limited to 2.5 mA. Because the
external ACC pin is capable of supplying significantly large amounts of current compared to the drain pump,
all 32 bits are available for programming with a single programming pulse. This is an enormous improvement
over the standard 5-bit programming. If the user is able to supply an external power supply and connect it to
the ACC pin, significant time savings are realized.
In order to enter the Accelerated Program mode, the ACC pin must first be taken to VHH (12 V ± 0.5 V) and
followed by the one-cycle command with the program address and data to follow. The Accelerated Chip
Program command is only executed when the device is in Unlock Bypass mode and during normal read/reset
operating mode.
In this mode, the write protection function is bypassed unless the PPB Lock Bit = 1.
The Accelerated Program command is not permitted if the Secured Silicon sector is enabled.
15.7
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard
program command sequence. The unlock bypass command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then
enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 14.4 on page 39 and Table 15.2
on page 52 show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care
for both cycles. The device then returns to reading array data.
Table 15.1 on page 43 illustrates the algorithm for the program operation. See Erase/Program Operations
on page 68 for parameters, and to Figure 24.8 on page 69 and Figure 24.9 on page 69 for timing diagrams.
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