參數(shù)資料
型號： S29C51001B
廠商： Electronic Theatre Controls, Inc.
英文描述： 1 MEGABIT (131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
中文描述： 1兆位（131072 × 8位）5伏的CMOS閃存
文件頁數(shù)： 10/16頁
文件大?。?/td> 7725K
代理商： S29C51001B
10
NOTES:
1.
2.
X = Don’t Care, V
IH
= HIGH, V
IL
= LOW. V
H
= 12.5V Max.
PD: The data at the byte address to be programmed.
Table 2. Command Codes
NOTES:
1.
2.
3.
4.
Top Boot Sector
Bottom Boot Sector
PA: The address of the memory location to be programmed.
PD: The data at the byte address to be programmed.
Disabling Boot Block Protection Lock
V
H
V
H
V
IL
X
X
V
H
X
Output Disable
V
IL
V
IH
V
IH
X
X
X
HIGH-Z
Command
Sequence
First Bus
Program Cycle
Second Bus
Program Cycle
Third Bus
Program Cycle
Fourth Bus
Program Cycle
Fifth Bus
Program Cycle
Six Bus
Program Cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Read
XXXXH
F0H
Read
5555H
AAH
2AAAH
55H
5555H
F0H
RA
RD
Autoselect
5555H
AAH
2AAAH
55H
5555H
90H
00H
40H
01H
01H
(1)
A1H
(2)
Byte
Program
5555H
AAH
2AAAH
55H
5555H
A0H
PA
PD(4)
Chip Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Sector Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
PA(3)
30H
Decoding Mode
CE
OE
WE
A
0
A
1
A
9
I/O
Chip Erase Cycle
The
S
29C51001T/
S
29C51001B features a chip-
erase operation. The chip erase operation is
initiated by using a specific six-bus-cycle
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).
The chip erase operation is performed
sequentially, one sector at a time. When the
automated on chip erase algorithm is requested
with the chip erase command sequence, the device
automatically programs and verifies the entire
memory array for an all zero pattern prior to erasure
The automatic erase begins on the rising edge of
the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is “1”.
Program Cycle Status Detection
There are two methods for determining the state
of the
S
29C51001T/
S
29C51001B during a
program (erase/program) cycle: DATA Polling
(I/O
7
) and Toggle Bit (I/O
6
).
DATA Polling (I/O
7
)
The
S
29C51001T/
S
29C51001B features DATA
polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
complement of the loaded data on I/O
7
. Once the
program cycle is completed, I/O
7
will show true
data, and the device is then ready for the next
cycle.
Toggle Bit (I/O
6
)
The
S
29C51001T/
S
29C51001B also features
another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O
6
toggling between 1 and 0. Once the program is
completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.
SyncMOS Technologies Inc.
S
29C5100
1
T/
S
29C5100
1
B
1
MEGABIT (
131,072
x 8
BIT)
5 VOLT CMOS FLASH MEMORY
S
29C51001T/
S
29C51001B
V1.0
February
2003
相關(guān)PDF資料
PDF描述
S29C51001T 1 MEGABIT (131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
S29C51001 1 MEGABIT (131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
S29C51004T90J 4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29C51001T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 MEGABIT (131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
S29C51004B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
S29C51004B12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
S29C51004B12P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
S29C51004B12T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4 MEGABIT (524,288 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
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