參數(shù)資料
型號(hào)： S29AL004D90BAI022
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 4 Megabit (512 Kx 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
中文描述： 256K X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： 8.15 X 6.15 MM, FBGA-48
文件頁(yè)數(shù)： 24/55頁(yè)
文件大?。?/td> 1481K
代理商： S29AL004D90BAI022
22
S29AL004D
S29AL004D_00_A1 February 18, 2005
A d v a n c e I n f o r m a t i o n
Figure 4, on page 24
illustrates the algorithm for the erase operation. See
Table 12 on page 41
for parameters, and
Figure 18, on page 43
for timing
diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command.
Table on page 24
shows the address and
data requirements for the sector erase command sequence.
The device does
not
require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 μs begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 μs, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 μs, the system need not monitor DQ3.
Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data.
The system must rewrite the
command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See
DQ3: Sector Erase Timer on page 29
). The time-out begins from the
rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. Note that a
hardware reset
during the
sector erase operation immediately terminates the operation. The Sector Erase
command sequence should be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to
Write
Operation Status on page 26
for information on these status bits.
Figure 4, on page 24
illustrates the algorithm for the erase operation. Refer to
Table 12 on page 41
for parameters, and to
Figure 18, on page 43
for timing
diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase oper-
ation and then read data from, or program data to, any sector not selected for
erasure. This command is valid only during the sector erase operation, including
the 50 μs time-out period during the sector erase command sequence. The Erase
Suspend command is ignored if written during the chip erase operation or Em-
bedded Program algorithm. Writing the Erase Suspend command during the
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