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參數(shù)資料
| 型號(hào)： | S2100 |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | 64-bit FUSE ROM |
| 中文描述： | 64位保險(xiǎn)絲光盤 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 83K |
| 代理商： | S2100 |
64-bit FUSE ROM
S-2100R
4
Seiko Instruments Inc.
Read Mode Operation
Counter Hold Mode Operation
By setting the CE/PE terminal to
“
L
”
level, the S-2100R enters the read mode. *
1
Next, adding an RST pulse causes the
contents of the memory bit of address 1 to be output at the DATA terminal; the rising of the RST pulse latches the data and
stabilizes it. *
2
Reading of addresses from 2 to 64 can be done by adding a CLK pulse sequentially after reading address 1. *
3
As soon as address 64 has been read, the COUNTER OUT terminal outputs
“
H
”
level. When it finishes reading address 64, it
does not accept any more CLK pulses and the counter does not operate. The data of address 64 is maintained till address 1 is
read by the RST pulse.
Figure 3 Read mode timing
Address 1 output
Address 3 output
Address 2 output
t
CES
t
ACC
t
CE
t
RC
t
ACC
t
CH
t
RC
t
RH
CE/PE
RST
CLK
DATA
Address 1 output
t
RS
t
RC
*1
When both the CLK and RST terminals are at
“
H
”
level.
When the RST terminal is at
“
L
”
level, the latch is transparent and the data is recognized by the rising of the RST pulse.
Data read by the CLK pulse is latched at its rising.
*2
*3
By setting the CE/PE terminal to
“
H
”
level, the S-2100R enters the counter hold mode and the DATA terminal becomes high
impedance.
In counter hold mode, the CLK and RST pulses which fall while the CE/PE terminal is at
“
H
”
level are recognized to be invalid
and there is no change in counter and data output. When the CE/PE terminal is set to
“
L
”
level again, it returns to the
condition in which it was before the counter hold mode.
*
4
Address M
output
Address M+1 output
Address M+1 output
t
CES
t
CRI
CE/PE
RST
CLK
DATA
t
WZ
t
CS
Figure 4 Counter hold mode timing
*
4
When both the CLK and RST terminals are at
“
H
”
level.
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