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參數(shù)資料
| 型號： | S2092 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Serial Backplane Retimer Device(帶片上頻率鎖相環(huán)的串行重定時芯片) |
| 中文描述： | 串行背板重定時器裝置（帶片上頻率鎖相環(huán)的串行重定時芯片） |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 132K |
| 代理商： | S2092 |
2
S2092
SERIAL BACKPLANE RETIMER DEVICE
July 10, 2000 / Revision A
S2092 OVERVIEW
The S2092 supports clock recovery from 2.488 Gbps
to 2.67 Gbps data rate. Differential serial data is input
to the chip at the specified rate, and clock recovery is
performed on the incoming data stream. An external
oscillator is required to minimize the PLL lock time.
Retimed data is output from the S2092.
Figure 2. S2092 Functional Block Diagram
2
LOCKDET
SERDATOP/N
REFCLKP/N
TESTCLK
LCKREFN
SERDATIP/N
LOOP
FILTER
VCO
CLOCK
DIVIDER
PHASE DETECTOR
LOCK
DETECTOR
SDN
CAP 1,2
REFSEL
TESTEN
RST
BYPASS
TESTOUT 1
TESTOUT 2
Suggested Interface Devices
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| S2092TT | 制造商:AppliedMicro 功能描述:Telecommunication IC |
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