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參數(shù)資料
| 型號： | S2042 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS |
| 中文描述： | 高性能串行接口電路 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 241K |
| 代理商： | S2042 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
14
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2043
Parameters
Transmitter Output Jitter Allocation
Description
Min
Max
Units
Conditions
T
1
T
2
T
3
T
4
T
5
T
CR ,
T
CF
T
SDR ,
T
SDF
T
6
T
DC
REFCLK to TCLK
Data setup w.r.t. REFCLK
Data hold w.r.t. REFCLK
Data setup w.r.t. TCLK
Data hold w.r.t. TCLK
TCLK rise and fall time
Serial data rise and fall
TCLK to TCLKN Skew
TCLK, TCLKN Duty Cycle
1.0
1.0
2.0
5
1
—
—
—
40
4.0
—
—
5.0
300
1
60
ns
ns
ns
ns
ns
ns
ps
ns
%
—
—
—
10% to 90%, tested on a sample basis.
20% to 80%, tested on a sample basis.
Tested on a sample basis.
—
T
JRMS
Serial data output random
jitter (RMS)
—
20
ps
RMS, tested on a sample basis.
Measured with 1010 pattern.
Measured with IDLE pattern.
—
100
ps
Peak-to-peak, tested on a sample basis.
Serial data output
deterministic jitter (p-p)
T
DJ
Table 5. AC Characteristics
Table 6. S2043 Receiver Timing
Parameters
Description
Min
Max
Units
Conditions
T
3
T
4
T
5
T
6
T
7
T
RCR ,
T
RCF
T
DR ,
T
DF
T
SDR ,
T
SDF
T
LOCK
Duty Cycle
Input Jitter
Tolerance
RCLK to RCLKN skew
Data set-up time
Data hold time
Data set-up time
Data hold time
RCLK rise and fall time
Data Output rise and fall time
Serial data input rise and fall
Data acquisition lock time @
<1.0625Gb/s
RCLK/RCLKN Duty Cycle
Input data eye opening
allocation at receiver input
for BER
≤
1E–12
—
3.0
1.5
2.5
7.5
—
—
—
—
40%
30%
1
—
—
—
—
5.0
5.0
300
2.4
60%
—
ns
ns
ns
ns
ns
ns
ns
ps
μ
s
bit time
Tested on a sample basis.
1062 Mbit/sec, 10-bit mode.
1062 Mbit/sec, 10-bit mode.
1062, 531 Mbit/sec, 20-bit mode.
531, 266 Mbit/sec, 20-bit mode.
1062, 531 Mbit/sec, 20-bit mode.
531, 266 Mbit/sec, 20-bit mode.
10% to 90%, tested on a sample basis.
10% to 90%, tested on a sample basis.
20% to 80%.
8B/10B IDLE pattern sample basis
As specified in Fibre Channel FC–PH
standard eye diagram jitter mask.
Note:
All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels (.8V or
2.0V). All TTL AC measurements are assumed to have the output load of 10pF.
Note:
All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output
data levels (.8V or 2.0V). All TTL AC measurements are assumed to have the output load of 10pF.
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