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參數(shù)資料
| 型號： | S2036 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Open Fiber Control（OFC）System(實現(xiàn)光纖控制（OFC）的系統(tǒng)) |
| 中文描述： | 開放光纖控制（OFC）的系統(tǒng)（實現(xiàn)光纖控制（大洋洲）的系統(tǒng)） |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 119K |
| 代理商： | S2036 |
5
S2036
OPEN FIBER CONTROL
State Machine
The state machine is implemented per the Fibre
Channel FC-PH document, Paragraph 6.2.3 and an-
nex I. The OFC time periods are user-selectable to
comply with the operating frequency of the serial
link. The selectable OFC time periods are seen in
Table 1. The pulse repetition time is fixed for both
25, 50, and 100 Mbyte applications to 10.1 seconds.
The inputs to the state machine are the loss of light
indicators (DC and AC) and the power-on reset. The
timing of the state machine transitions is controlled
by the decode times. The timing of the laser control
signals will not necessarily be synchronous to the
system clock because of the long counter times involved.
Link Initialization
Following a power-on-reset cycle, the OFC device
will be in the Stop State as defined in the Fibre
Channel Standard. The default state for the internal
loopback control is loopback active. A Control/Status
Write cycle is required together with a logic high on
the LOOPEN input in order to place the OFC in the
Reconnect State allowing the repetitive pulsed out-
put operation. The required timing for this write cycle
is shown in Figure 5.
Reference Clock Select
The reference clock is user-selectable to be 53 MHz
or 26 MHz. The reference clock input is divided by
four if a 53-MHz clock is used, or by two for a 26-
MHz clock so that all state machine and counter
clocks operate at 13 MHz. Refer to Figure 3 and
Figures 7 through 10 for suggested connections.
Clock Detect
The clock detect circuitry compares the reference
clock input and the ring oscillator. If the ring oscilla-
tor and the reference clock frequencies do not
compare as selected by CTRL2, CTRL1/1B, and
CTRL0/0B, the laser is disabled to prevent it from
staying on or increasing the laser duty cycle.
De-Glitch Logic
The de-glitch logic debounces the power-on reset
and the link control pin to eliminate potential glitching
of the laser control lines.
Counter
The two counter blocks are redundant functions
which generate the selected decode timing used by
the state machines. (See Table 1 for OFC time peri-
ods.) One of the counters is used as the lower part
of the 10.1 sec pulse repetition timer.
Pulse Repetition Timer
The pulse repetition timer generates the 10.1 sec
decode timer used by the state machines. In test
mode it is broken up into three counter stages which
is output on the PRT<0> pin.
Figure 4. Loopback Enable Write Access
0→
OFC ENABLED , 1
→
LASER OFF
LOOPEN
CSRW
Trwsu
Tcsmpw
Trwh
Tch
Tcsu
CSSTROBE
Symbol
Description
Min
Max
Units
Trwsu
CSRW setup time before CSSTROBE rising edge
5
ns
Trwh
CSRW hold time after CSSTROBE rising edge
5
ns
Tcsu
LOOPEN setup time before CSSTROBE rising edge
5
ns
Tch
LOOPEN hold time after CSSTROBE rising edge
5
ns
Tcsmpw
CSSTROBE minimum pulse width
15
ns
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