參數(shù)資料
型號： S1R72C05B10
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA121
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TFBGA-121
文件頁數(shù)： 30/49頁
文件大?。?/td> 545K
代理商： S1R72C05B10
7. ELECTRICAL CHARACTERISTICS
S1R72C05*** Data Sheet (Rev.1.00)
EPSON
31
7.4.4.6 Ultra DMA Write Timing
XHCS[1:0](O)
HDA[2:0](O)
HDMARQ(I)
XHDMACK(O)
XHIOW(O)
HDD[15:0](O)
HIORDY(I)
XHIOR(O)
valid
T381
T384
T385
T386
T387
T388
T389
T38a
T389
Initiating
Device Pausing
T382
T38b
(STOP)
(HSTROBE)
(XDDMARDY)
Code
Description
Min.
Typ.
Max.
Units
T381
80
-
ns
T382
65
-
ns
T384
28
-
40
ns
T385
IDE spec.
tLI
-
IDE spec.
tLI
ns
T386
20
-
ns
T387
-
(cyc+1) *
16.7
-
ns
T388
-
(cyc+1) *
16.7
-
ns
T389
-
ns
T38a
-
ns
T38b
20
-
38
ns
-
(cyc+2) *
16.7
-
T389 * 2
Data transfer direction:
S1R72C05
DATA
XHCS
↑, HDA → XHDMACK ↓
Address setup time
HDMARQ
↑ → XHDMACK ↓
XHDMACK response time
XHDMACK
↓ → XHIOW ↓
Envelope time
XHIOW
↓ → HIORDY ↓
Restricted interlock time
HIORDY
↓ → XHIOR ↓
Unrestricted interlock time
HDD
→ XHIOR ↓
Data setup time
XHIOR
↓ → HDD
Data hold time
XHIOR
→ XHIOR
XHIOR cycle time
XHIOR
→ XHIOR
XHIOR cycle time x2
HIORDY ↑ → XHIOR
Final STROBE time
*1: cyc = UltraDMAcycle
For detailed information, refer to “IDE Ultra-DMA Transfer Mode” in the register description.
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