參數(shù)資料
型號： S1R72C05B10
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA121
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TFBGA-121
文件頁數(shù)： 24/49頁
文件大?。?/td> 545K
代理商： S1R72C05B10
7. ELECTRICAL CHARACTERISTICS
S1R72C05*** Data Sheet (Rev.1.00)
EPSON
25
7.4.4 IDE I/F Timing
7.4.4.1 PIO Read Timing
Code
Description
Min.
Typ.
Max.
Units
T321
-
0
-
ns
T322
-
0
-
ns
T323
80
-
ns
T324
-
(AP+4) *
16.7 - 3
-
ns
T325
-
(NP+4) *
16.7 + 3
-
ns
T326
50
-
ns
T327
10
-
ns
T328
0
-
ns
T329
-
25
ns
stable
XHCS0(O)
HDA[2:0](O)
XHIOR(O)
HDD[15:0](I)
HIORDY(I)
T324
T321
T326
T325
T322
T327
T328
T329
T323
Data transfer direction:
S1R72C05
DATA
XHCS0
↓ → HDA
HDA output delay time
XHCS0
↑ → HDA
HDA hold time
XHCS0
↓ → XHIOR ↓
XHCS0 setup time
XHIOR
↓ → XHIOR ↑
XHIOR assert pulse width
XHIOR
↑ → XHIOR ↓
XHIOR negate pulse width
XHIOR
↑ → XHCS0 ↑
XHCS0 hold time
HDD
→ XHIOR ↑
Data setup time
XHIOR
↑ → HDD
Data hold time
HIORDY
↑ → XHIOR ↑
XHIOR output delay time
*1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth
For detailed information, refer to “IDE Transfer Mode” in the register description.
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