- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄192292 > S1M8836X01-G0T0 PLL FREQUENCY SYNTHESIZER, 1000 MHz, CQCC24 PDF資料下載
參數(shù)資料
| 型號： | S1M8836X01-G0T0 |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1000 MHz, CQCC24 |
| 封裝： | 3.50 X 4.50 MM, QFN-24 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 234K |
| 代理商： | S1M8836X01-G0T0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
5
PIN DESCRIPTION
Pin No.
Symbol
I/O
Descriptions
1
V
DDRF
–
RF PLL power supply (2.7V to 4.0V). Must be equal to V
DDIF.
2
VpRF
–
Power supply for RF charge pump. Must be
≥ V
DDRF and VDDIF.
3
CPoRF
O
RF charge pump output. Connected to an external loop filter.
4
DGND
–
Ground for RF PLL digital circuitry.
5
finRF
I
RF prescaler input. Small signal input from the external VCO.
6
finRF
I
RF prescaler complementary input. For a single-ended output RF VCO, a bypass
capacitor should be placed as close as possible to this pin and be connected
directly to the ground plane.
7
GNDRF
–
Ground for RF PLL analog circuitry.
8
V
DDRFa
–
PLL power supply (2.7V to 4.0V) for RF analog (prescaler). Must be equal to V
DDRF
9
OSCin
I
Oscillator input to drive both the IF and RF R counter inputs.
10
foLD
O
Multiplexed output of N or R divider and RF/IF lock detect.
11
RF_EN
I
RF PLL Enable (Enable when HIGH, Power down when LOW). Controls the RF PLL
to power down directly, not depending on a program control. Also sets the charge
pump output to be in TRI-STATE when LOW. Powers up when HIGH depends on
the state of RF_CTL_WORD.
12
IF_EN
I
IF PLL Enable (Enable when HIGH, Power-down when LOW). Controls the IF PLL
to power down directly. The same as RF_EN except that power-up depends on the
state of IF_CTL_WORD.
13
CLOCK
I
CMOS clock input. Data for the various counters is clocked into the 22-bit shift
register on the rising edge.
14
DATA
I
Binary serial data input. Data entered MSB (Most Significant Bit) first.
15
LE
I
Load enable when LE goes HIGH. High impedance CMOS input.
16
GNDIF
–
Ground for IF analog circuitry.
17
finIF
I
IF prescaler complementary input. For a single-ended output IF VCO, a bypass
capacitor should be placed as close as possible to this pin.
18
finIF
I
IF prescaler input. Small signal input from the VCO.
19
DGND
–
Ground for IF PLL digital circuitry.
20
CPoIF
O
IF charge pump output. Connected to an external loop filter.
21
VpIF
–
Power supply for IF charge pump. Must be
≥ V
DDRF and VDDIF.
22
V
DDIF
–
IF PLL power supply (2.7V to 4.0V). Must be equal to V
DDRF.
23
OUT1
O
Programmable CMOS output. Level of the output is controlled by W2[19] bit.
24
OUT0
O
Programmable CMOS output. Level of the output is controlled by W2[18] bit.
In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous
switches between active low and tri-state.
相關PDF資料 |
PDF描述 |
|---|---|
| S1P-SLV | 1 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP |
| S1T0567X01-D0B0 | TELECOM, TONE DECODER CIRCUIT, PDIP8 |
| S1U2-12-RC | 500 MHz - 2000 MHz RF/MICROWAVE SGL POLE SGL THROW SWITCH, 1.5 dB INSERTION LOSS |
| S2004VS2 | 4 A, 200 V, SCR, TO-251 |
| S2010F126 | 10 A, 200 V, SCR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S1M8837 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
| S1M8837X01-G0T0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
| S1MA | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Standard Surface Mount Glass Passivated Rectifier |
| S1MA-E3/5AT | 功能描述:整流器 1.0 Amp 1000 Volt 30A IFSM @ 8.3ms RoHS:否 制造商:Vishay Semiconductors 產(chǎn)品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復時間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
| S1MA-E3/61T | 功能描述:整流器 1.0 Amp 1000 Volt RoHS:否 制造商:Vishay Semiconductors 產(chǎn)品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復時間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。