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參數(shù)資料
| 型號(hào)： | S1M8831A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
| 中文描述： | 分?jǐn)?shù)N射頻/整數(shù)N如果雙鎖相環(huán) |
| 文件頁(yè)數(shù)： | 25/32頁(yè) |
| 文件大?。?/td> | 248K |
| 代理商： | S1M8831A |
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8831A/33
25
Programmable Counter Reset Control
Control Words
IF_CTL_WORD
Control Bits
IF_N[21]
Acronym
IF_CNT_RST
LOW (0)
Normal
Operation
Normal
Operation
HIGH (1)
IF Counter
Reset
RF Counter Reset
Comments
IF
RF_CTL_WORD
RF_N[23]
RF_CNT_RST
RF
Counter Reset Mode Resets R & N Counters.
RF Fractional-N Selection
Control Words
RF_CTL_WORD
Control Bits
RF_N[21]
Acronym
Frac-N_SEL
LOW (0)
Reserved
HIGH (1)
Comments
RF; PLL Mode
Selection
Fractional-N Mode
CMOS Output Control
Control Words
CMOS
Control Bits
RF_N[20]
RF_N[19]
RF_N[18]
Acronym
Speedy Lock
OUT1
OUT0
LOW (0)
CMOS Output
Voltage LOW
Voltage LOW
HIGH (1)
Comments
Speedy Lock Mode
Voltage HIGH
Voltage HIGH
Pin #23
Pin #24
In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low
and a tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a
low impedance ( < 150
) while a high charge pump gain (
≥
8X) is selected and otherwise to a tri-state. For using
a programmable CMOS output, the CMOS output bit(RF_N[20] = LOW) should be activated and then the desired
logic level should be programmed with the control bits RF_N[18] for OUT0 and RF_N[19] for OUT1.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S1M8831A/33 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
| S1M8831A01-G0T0 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
| S1M8833 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
| S1M8833X01-G0T0 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
| S1M8836 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
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