參數(shù)資料
型號: S1D2502B01
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
中文描述: 視頻放大器合并OSD處理器的顯示器
文件頁數(shù): 55/61頁
文件大小: 722K
代理商: S1D2502B01
S1D2502B01 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
54
Preliminary
I
2
C Control Line (SCL, SDA Line)
I
2
C communication noise (noise generated in the OSD display pattern when data is transmitted in the I
2
C line) may
be generated because of an I
2
C control line that passes near the analog block. The I
2
C control lines near
S1D2502B01 must be separated from the analog block as much as possible.
Furthermore, the I
2
C bus interference can be prevented by inserting a series resistor in the line.
Horizontal Flyback Signal
Display jittering can be generated if the horizontal signal (HFLB) input to S1D2502B01 is not a clean signal.
We recommend a short path and shielded cable for obtaining a clean signal.
Generally, the input horizontal signal (HFLB) is generated by using a high voltage horizontal flyback signal. The
effect from the high voltage flyback signal can be reduced by separating the R115 and R117 GND, which
determines the flyback signal slice level, from the transistor GND, which generates the actual S1D2502B01 input
horizontal signal. Furthermore, the flyback signal sharpness must be maintained by minimizing the values of R115,
R116 and R117 resistors, which set the horizontal signal slice level. values.
(R115, R116, R117: Refer to application circuit )
HFLB Input Signal Generator
You can correct the circuit by reducing the resistors that sets the slice level of the horizontal signal in the HFLB-
generating circuit.
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