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參數(shù)資料
| 型號(hào)： | S1D2502B01 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS |
| 中文描述： | 視頻放大器合并OSD處理器的顯示器 |
| 文件頁數(shù)： | 28/61頁 |
| 文件大?。?/td> | 722K |
| 代理商： | S1D2502B01 |
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VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502B01
27
Preliminary
Tabel 4. Register Description (Continued)
Registers
Frame Control
Registers — 1
(Row 15,
Column 01)
Bits
Description
CH5 — CH0
(bit 5 — 0)
Character height control
While the purpose of VZ[1:0] (vertical character height) is to control the
absolute size of the character, the purpose of CH[5:0] (Character Height) is
to output OSD of a uniform size even if the resolution changes. If you adjust
the value in the range of CH = 18 — CH = 63, each line's repeating number
is decided (standard height CH = 18 is the reference value), by which the
line is repeated. For more information on repeating number selection, refer
to character height.
Selection of the FBLK output pin's configuration
Unlike pin description's FBLK, if this bit is '0', the FBLK pin output is high
while the character and raster are being displayed and the character and
raster are output as they are. If this bit is '1', the FBLK pin output becomes
high only when character is being displayed, so only the character is
output. Refer to 'Figure 11. Character/raster signal part.
Resolution control (dots/line)
FBLK
(bit 6)
dot1, dot0
(bit 9, 8)
As shown above, the number of dots per horizontal line is decided by a
combination of these two bits.
Horizontal frequency
PLL's horizontal frequency is decided by the combination of these 3 bits.
This is related to the selection of DOT[1:0], so you can't numerically
express the frequency range with only the HF[2:0] selection. For more
information, please refer to HF Bits Selection.
Full range PLL
If this bit is '1', the OSD_PLL block's VCO operates at full range (4.8MHz -
96MHz). If it is ’0', it operates within the region decided by the HF bit [C:A]
explained above. if you can’ optimize OSD screen decided by the HF bit in
the high region, you may set the FPLL bit to ‘1’
HF2— HF0
(bit C — A)
FPLL
(bit D)
Dot1
Dot0
No. of Dots
0
0
320 dots/line
0
1
480 dots/line
1
0
640 dots/line
1
1
800 dots/line
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PDF描述 |
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| S1D2502B01-D0B0 | VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS |
| S1D2503X01-D0B0 | Circular Connector; Body Material:Aluminum; Series:PT01; No. of Contacts:25; Connector Shell Size:20; Connecting Termination:Solder; Circular Shell Style:Cable Receptacle; Circular Contact Gender:Socket; Insert Arrangement:20-25 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1D2502B01-D0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS |
| S1D2503X01-D0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:I2C BUS CONTROLLED R/G/B VIDEO AMPLIFIER FOR MONITORS |
| S1D2504A01 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:I2C BUS CONTROLLED R/G/B VIDEO AMPLIFIER |
| S1D2504A01-D0B0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:I2C BUS CONTROLLED R/G/B VIDEO AMPLIFIER |
| S1D2506A01-D0B1 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:I2C BUS CONTROLLED R/G/B VIDEO AMPLIFIER FOR MONITORS |
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