參數(shù)資料
型號: S1C621A0F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 126/161頁
文件大小: 1037K
代理商: S1C621A0F0A0100
I-42
EPSON
S1C621A0 TECHNICAL HARDWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Remote LED Control)
Once values have been set in these registers, subsequent
cycles will be generated with the same division ratio. Note
that they can be set only while the REM circuit is OFF
(except for initialization). (An error will result if the regis-
ters are set at any other time.) Figure 3.9.7 shows the
τ-
waveform with the division ratio 2 set at 1/12.
Fig. 3.9.7
τ-waveform
When the REMC is set to 0, the REM circuit stops syn-
chronously with
τ. This timing is shown in Figure 3.9.8.
Fig. 3.9.8
REM Circuit Stop
Timing
Maximum of 384 machine cycles* are required until the
REM circuit stops after the REMC is set to 0. Even if the
CPU clock is changed from OSC3 to OSC1 after the
REMC = 0, OSC3 must not be turned OFF before the
REM circuit stops.
*
This time depends on the value of the set
τ cycle. If a shorter τ
cycle is set, the maximum time required for the REM circuit to
stop after REMC = 0 is shortened.
Carrier
- waveform
τ
Carrier
- waveform
τ
Stop synchronously with
REMC
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