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參數(shù)資料
| 型號(hào)： | S1800B-FREQ(T)-OUT24 |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 50 MHz, CMOS/LSTTL OUTPUT |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 101K |
| 代理商： | S1800B-FREQ(T)-OUT24 |
SaRonix
Crystal Clock Oscillator
3.3 & 5V, HCMOS, TTL, SMD
S1800 / S1803 / S1850 Series
Technical Data
All specifications are subject to change without notice.
DS-181
REV F01
Tri-State Logic Table
Test Circuit
Scale: None (Dimensions in
)
mm
inches
Pad 1 Input
Logic 1 or NC
Logic 0 or GND
Pad 3 Output
Oscillation
High Impedance
Required Input Levels on Pad 1:
Logic 1 = 2.2V min
Logic 0 = 0.8V max
Package Details
7.5
.295
max
5.2
.205
max
1.15
.043
1.4
.055
Pad 2
(GND)
Pad 1
(Tri-State
Control)
2.6
.102
5.08
.200
Pad 3
(OUT)
Pad 4
(VDD)
1.1
.043
max
Output Waveform
SaRonix
Frequency
Date Code
S 5 C
5 = S1800
9 = S1803
B = S1850
Stability Tolerance
Marking Format*
CL = S1800/S1803: 15 pF
S1850: 50 pF to 50 MHz
30 pF, 50+ to 70 MHz
20 pF, 70+ to 80 MHz
(Note A)
POWER
SUPPLY
mA
M
V M
TEST
POINT
OUT
VDD
OSCILLATOR
GND
Pad 2
Pad 1
Pad 4
Pad 3
0.1F
TRI-STATE INPUT
Note A: CL includes probe and fixture capacitance
Recommended Land Pattern
*Exact location of items may vary
1.8
.071
2.0
.079
4.2
.165
5.08
.200
YY WW
**External high frequency power supply
decoupling required.
**
2.5 VDC
1.5 VDC
0.5 VDC
Tf
Tr
HCMOS
TTL
SYMMETRY
GND
VDD
LOGIC 0
20% VDD
50% VDD
80% VDD
LOGIC 1
12
43
SaRonix 141 Jefferson Drive Menlo Park, CA 94025 USA 650-470-7700 800-227-8974 Fax 650-462-9894
1.0
.039
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