參數(shù)資料
型號: S-80841CLMC-B62T2G
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封裝: LEAD FREE, SOT-23, 5 PIN
文件頁數(shù): 16/59頁
文件大?。?/td> 579K
代理商: S-80841CLMC-B62T2G
SUPER-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR
Rev.5.0_00
S-808xxC Series
Seiko Instruments Inc.
23
Operation
1. Basic Operation: CMOS Output (Active Low)
1-1.
When the power supply voltage (VDD) is higher than the release voltage (
+VDET), the Nch transistor is
OFF and the Pch transistor is ON to provide VDD (high) at the output. Since the Nch transistor N1 in
Figure 17
is OFF, the comparator input voltage is
C
B
A
DD
C
B
R
V
)
R
(
+
+
.
1-2.
When the VDD goes below
+VDET, the output provides the VDD level, as long as the VDD remains above
the detection voltage
VDET. When the VDD falls below VDET (point A in Figure 18), the Nch transistor
becomes ON, the Pch transistor becomes OFF, and the VSS level appears at the output. At this time
the Nch transistor N1 in Figure 17 becomes ON, the comparator input voltage is changed to
B
A
DD
B
R
V
R
+
.
1-3.
When the VDD falls below the minimum operating voltage, the output becomes undefined, or goes to the
VDD when the output is pulled up to the VDD.
1-4.
The VSS level appears when the VDD rises above the minimum operating voltage. The VSS level still
appears even when the VDD surpasses
VDET, as long as it does not exceed the release voltage +VDET.
1-5.
When the VDD rises above
+VDET (point B in Figure 18), the Nch transistor becomes OFF and the Pch
transistor becomes ON to provide VDD level at the output.
VREF
Pch
Nch
N1
RC
RB
RA
+
OUT
VSS
VDD
*1
*1.
Parasiteic diode
Figure 17 Operation 1
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