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| 型號： | S-7600A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | Hardware Specification (TCP/IP Network Stack LSI) |
| 中文描述： | 硬件規(guī)格（TCP / IP網(wǎng)絡(luò)堆棧大規(guī)模集成電路） |
| 文件頁數(shù)： | 21/60頁 |
| 文件大小： | 371K |
| 代理商： | S-7600A |
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TCP/IP Network Stack LSI
S-7600A
Hardware Specification
Revision 1.3
Seiko Instruments Inc.
5-4
5.2.2. x80 Family MPU Mode
This mode is selected by pulling the
C86
input pin “L” and the
PSX
input pin “H”. In this mode, the
address and data are muxed onto a single 8-bit bus. All cycles start with the address placed on the bus.
This address is then latched internally on the rising edge of
WRITEX
. The
RS
pin “L” indicates that the
WRITEX
strobe is for the address phase. In the next phase, data is either written or read by generating
WRITEX
or
READX
strobe. The MPU interface logic will assert the
BUSYX
signal after
READX
or
WRITEX
strobes are de-asserted. The
BUSYX
signal is de-asserted after the S-7600A complete a read
or writes operation. The MPU samples the
BUSYX
signal before starting a new cycle. The MPU can
initiate a new cycle after the
BUSYX
signal gets de-asserted.
5.2.2.1. Write Cycle Timing
Figure 5-3
x80 Family MPU Write Cycle Timing
Symbol
T
CYC8
T
AH8
T
AW8
T
DS8
T
DH8
T
CC8
T
BD8
T
BC8
T
BOD8
Description
System Cycle Time
Address Hold Time
Address Setup Time
Data Setup time
Data Hold Time
Control Pulse Width
BUSYX Delay Time
BUSYX Pulse Width
BUSYX Output Disable Time
NOTES:
CLK is the clock of S-7600A
Timing is specified of 50% of the signal waveform.
Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-5
x80 Family MPU Write Cycle Timing
Min
100 ns
20ns
20ns
20ns
20 ns
40 ns
2CLK
Max
1.9CLK
30ns
-
Notes
CL=80pF
CL=80pF
30ns
CS
READX
CLK
BUSYX
WRITEX
RS
SD7 to 0
T
AH8
T
AW8
T
CC8
T
DH8
T
DS8
T
BD8
T
BC8
T
DH8
T
AH8
T
AW8
T
CYC8
T
CC8
T
DS8
T
BOD8
Address
read
Data
read
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