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參數資料
| 型號： | S-2100R |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | 64-bit FUSE ROM(64位熔絲ROM) |
| 中文描述： | 64位保險絲光盤（64位熔絲光盤） |
| 文件頁數： | 7/9頁 |
| 文件大?。?/td> | 63K |
| 代理商： | S-2100R |
64-bit FUSE ROM
S-2100R
6
Seiko Instruments Inc.
Input Priority
In read mode, priority is given to either the CLK or RST terminal, whichever is entered first. Whichever pulse is input earlier is
recognized to be valid from the rising till the end of the operation. If the pulse input later is at “L” level, the signal is ignored, even
though the effective pulse input earlier rises. *
9
If the CLK and RST pulses are input, the mode shifts from read mode to counter hold mode when both the CLK and the RST
terminals go to “H” level. *
10
If the CLK and RST pulses which are input in the counter hold mode are still at “L” level after setting the CE/PE terminal to “L”
level, these CLK and RST terminals are ignored. The mode shifts to read mode and data which is held before the shift is output
at the DATA terminal. *
11
In program mode, inputting the DATA terminal before the CE/PE terminal goes to “H” level is prohibited. Also, charging the
writing voltage from the P
D
/V
PP
terminal is prohibited when the CE/PE terminal is at “L” level. In program mode, input to the
DATA terminal muse be decided before charging the writing voltage. *
12
*
9
*
10
The counter hold mode is entered when reading of the CLK and RST pulses has been finished and DATA output has been
stabilized .
*
11
No more CLK or RST pulses are accepted unless both the CLK and RST terminals are at “H” level.
*
12
If data input is changed while writing voltage is supplied, the S-2100R does not accept the changed data.
Input of the CLK and RST pulses is not recognized as valid unless both pulses are input at “H” level.
Notes
Memory should not be accessed for at least 10
μ
s after voltage is supplied and goes to V
DD
.
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