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參數(shù)資料
| 型號(hào)： | RTL8309SB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| 中文描述： | 單芯片9口10/100Mbps開關(guān)控制器 |
| 文件頁數(shù)： | 85/115頁 |
| 文件大?。?/td> | 866K |
| 代理商： | RTL8309SB |
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RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
70
Track ID: JATR-1076-21 Rev. 1.4
8.2.4.
Backpressure
The RTL8309SB provides two methods of preventing packet congestion when resources are about to be used up. The first is
by colliding incoming packets when the packets are going to a congested port. The second is by sending preambles to defer
other station’s transmissions.
Backpressure: When the switch is overloaded it will assert a jam pattern to collide incoming packets until the congestion
condition of the destination port is resolved. The 48 pass 1 mechanism prevents the port being partitioned by excessive
collisions. The RTL8309SB will forward one packet successfully after 48 forced collisions. This method carries some risk
since the resource may not be available after 48 forced collisions. If the 48 pass 1 function is turned off, the RTL8309SB will
always collide incoming packets with a jam pattern.
By deferring, the RTL8309SB sends preambles to defer other stations’ transmissions. To avoid jabber and excessive deference
as defined in IEEE 803.3, the RTL8309SB will pull down the carrier sense signal for a short time and then raise it up it
quickly. This short silence time is to prevent other stations seizing the medium and sending packets out. If there are packets to
send out during the carrier sense rising up period, carrier sense flow control will be replaced by those packets. After the
packets are sent, carrier sense rises up again, repeating the pattern until the system is available.
8.2.5.
UTP Port Status Configuration
The RTL8309SB supports flexible status configuration via strapping pins for each PHY, En_ANEG, En_FCTRL,
Force_Duplex, and Force_Speed, on a group basis. These pins are used to assign the initial values to PHY register 0 and 4
upon reset. The configuration parameters set by these four strapping pins globally control the abilities of each port. For
advanced applications requiring configuration on a per-port basis, a serial EEPROM should be attached.
If auto negotiation is enabled by strapping pin ‘En_ANEG’, the link status is determined by the result of the auto negotiation
process. The default configuration of the RTL8309SB is all abilities enabled (the content of the PHY registers will be
Reg0.12=1, Reg4.5=1, Reg4.6=1, Reg4.7=1, Reg4.8=1, and Reg4.10=1). If auto negotiation is disabled by EN_ANEG, the
link speed and duplex mode is forced by strapping pins, Force_Duplex and Force_Speed. These two pins have no effect if auto
negotiation is enabled.
8.2.6.
MII Port (The 9th Port)
The RTL8309SB is an 8-port Fast Ethernet switch with one extra MII port for specific applications. It integrates embedded
SRAM for packet storage, nine MAC, and eight physical layer transceivers for 10Base-T and 100Base-TX, into a single chip.
MII Port Operating Mode
The MII port only provides a MAC part to support the MII interface for connection with an external MAC or PHY. Two
strapping pins, MII_MODE[1:0], are used to configure this interface to act as MII PHY mode, SNI PHY mode, or MII MAC
mode to work with the external MAC of a routing engine, PHY of a HomePNA, or other physical layer transceivers
.
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