參數(shù)資料
型號(hào)： RSC-4128
廠商： Electronic Theatre Controls, Inc.
英文描述： Speech Recognition Processor
中文描述： 語(yǔ)音識(shí)別處理器
文件頁(yè)數(shù)： 31/49頁(yè)
文件大?。?/td> 690K
代理商： RSC-4128
Data Sheet
RSC-4128
31
P/N 80-0206-J
2004 Sensory Inc.
PWM timing for TenBits=1
prescaler=4
280
512
70
27.9 kHz
1 H / 511 L
383 H / 129 L
447 H / 65 L
511 H / 1 L
Item
nsec/clock (period ctr)
CLK1 clocks per period
nsec/clock (data ctr)
PWM frequency
pulse for data=001
pulse for data=17F
pulse for data=1BF
pulse for data=1FF
prescaler=6
420
768
140
18.6 kHz
2 H / 766 L
766 H / 2 L
-- n/a --
-- n/a --
prescaler=7
490
896
140
15.97 kHz
2 H / 894 L
766 H / 130 L
894 H / 2 L
-- n/a --
Additional considerations using the PWM for 10-bit Data
The 14.3 MHz CLK1 clock rate of the RSC-4128 is not fast enough to provide PWM synchronization with 10-bit
8kHz or 9.3 kHz data. To understand this, consider a PWM rate of 8 kHZ (125 microsec). To output 10 bits (9 bits
plus sign) during this interval, a source must provide 512 clocks, giving a source rate of 125000/512 = 244 nsec.
The CLK1 period is 70 nsec, so the relationship between the source clock and CLK1 is 244/70 = 3.5, which is not
an integer. So the source clock cannot be derived simply from CLK1.
The RSC-4128 application developer should address this issue by using a “near-10-bit” resolution, as follows. The
TenBits bit is
set
in the “pwmCtl” register, and the prescaler is programmed to 7 to produce a PWM frequency of
15.98 kHz (62.57 microseconds). During this interval there will be 62570/70 = 894 CLK1 clocks, or 894/2 (=447)
data counter clocks. The number 447 thus represents the largest possible count that can be loaded into the data
value counter. The range of allowable values is from –447 to +447. Any larger value would produce the same
output of the PWM pulse “on” for the entire duration of the PWM period. Thus 447 represents “full scale” of the
PWM. If all 10-bit data values are then scaled to a maximum of +/-447, the PWM will provide full-scale swing and
(close-enough) synchronization at 8 kHz. The actual number of bits in the data is log2(447 – (-447)) = 9.8 bits. The
developer must ensure that the value programmed in the data value counter must not exceed the range of –447 to
+447. Sensory Speech 7 provides PWM output utilities for speech and music that manage the PWM for the
developer, if so desired. (See “Sensory Speech 7 Technology Library Manual”)
PWM powerdown
The PWM may be independently powered down by programming the register D7.Bit 0 to “0” (“pwmCtl” register,
“pwm_on” bit). When the PWM is off, the PWM outputs PWM0 and PWM1 are in a high-Z state and pulled up by
internal 10K resistors. The PWM must be explicitly turned off before setting “pdn” equal to 1 to achieve the lowest
powerdown current.
Comparator Unit
The Comparator Unit consists of 2 analog comparators designated “A” and “B”, a programmable voltage reference,
selection circuitry, and two registers – the Comparator Control register (“cmpCtl”) and the Comparator Reference
(“cmpRef”). Register “cmpCtl” configures the comparator unit and provides the digital comparator outputs. Bits [2:0]
are used to select from one of eight comparator configurations, in which some or all of P2.0-P2.4 may be analog or
digital inputs. (See “RSC-4128 Comparator Unit” figure; “A” denotes analog input and “D” denotes digital input) Bits
[3:0] are read-write.
Register “cmpRef” controls the Comparator Reference Voltage. The unit can provide level information under
software control about 4 external analog signals. All external signals connected to the comparator inputs must be
between Vss and Vdd.
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