
RSC-4128
Data Sheet
(high) state ensures minimum power consumption as a default beginning. Sixteen of these pins (Ports P0 and P1)
can also be configured as inputs to control IO Wakeup events. (see “Power and Wakeup Control” section).
P2.0, P2.1, P2.3, and P2.4 can be configured as comparator inputs. P2.2 can be configured as a comparator
reference. Some or all of P2.0-P2.4 can be configured as digital inputs by the use of the “cmpCtl” register (register
D4) Bits[2:0] (see “Comparator Unit” section)
Note: When configuring P2.0-P2.4 as digital inputs the associated weak pull-up should be selected as shown
above.
P0.0 and P0.2 can be configured as External Interrupts (see “Interrupts” section). P0.1 can be configured in input
mode as a gate for an external event counter. (See “Timers/Counters” Section)
Registers E5 (“p0In”) and E4 (“p0Out”), E1(“p1In”) and E0 (“p1Out”), and DD (“p2In”) and DC (“p2Out”), provide
paths for data input and data output on P0, P1 and P2, respectively. The input registers are actually buffers which
record the value at the ports at the time they are read. The output registers latch the data written to them and
express it on the ports when the ports are configured as an output.
Following is a summary of the general purpose I/O control registers:
Register
0DCH Read/Write
P2[0:7] (port 2) output register. Cleared by reset.
0DDH Read
Port 2 input.
0DEH Read/Write
Port 2 Control Register A. Cleared by reset.
0DFH Read/Write
Port 2 Control Register B. Bits[7:5] cleared by reset.
Bits[4:0] set by reset
0E0H Read/Write
P1[0:7] (port 1) output register. Cleared by reset.
0E1H Read
Port 1 input.
0E2H Read/Write
Port 1 Control Register A. Cleared by reset.
0E3H Read/Write
Port 1 Control Register B. Cleared by reset.
0E4H Read/Write
P0[0:7] (port 0) output register. Cleared by reset.
0E5H Read
Port 0 input.
0E6H Read/Write
Port 0 Control Register A. Cleared by reset.
0E7H Read/Write
Port 0 Control Register B. Cleared by reset.
14
P/N 80-0206-J
2004 Sensory Inc.
GPIO during powerdown
GPIO should be put in input mode and a known state (e.g. light pull-up) whenever possible to conserve power, and
especially in powerdown mode to achieve the specified minimum supply current consumption.
Memory Addressing
The RSC4128 can address up to 2MBytes with a combination of 128Kbytes of default internal ROM and/or optional
external ROM, RAM or flash memories,
without additional decoding circuitry
. This is accomplished with 16 address
outputs, A[15:0], and up to 4 extended address outputs A[19:16]. There are two different memory spaces of up to
1MBbyte each: Constant/Code Space and Data Space. (“Constant” Space is referred to as “Const” space in
assembly and C-Data space in C) Data Space can be read or written. Constant/Code Space is typically read-only.
The RSC-4128 includes an external memory interface that allows connection with memory devices for storage of
speaker-dependent speech recognition templates, audio record/playback data storage, extended durations of
speech and music synthesis beyond the storage capabilities of on chip ROM, and code storage for the RSC4000
ROMless version. Thirty-four (34) pins are used to provide a parallel bus interface between the processor and
external ROM, EPROM, SRAM, or FLASH, for die and 100LQFP-packaged versions. An example of this parallel
bus usage is provided in the Reference Schematic 1-2. The RSC-4128 external memory interface has been
improved for ATD-type memories. The external address lines remain stable during instruction cycles that access
internal RAM or ROM. The –RDR and –RDF signals go high when not actively reading. The condition of the
external data lines is weak pull-up when not accessing the external bus. (See “DC Characteristics” section for bus
electrical characteristics.)