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參數(shù)資料
| 型號(hào)： | RNA50C27AUS |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | CMOS System-Reset IC |
| 中文描述： | 的CMOS系統(tǒng)復(fù)位IC |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 91K |
| 代理商： | RNA50C27AUS |
RNA50C27AUS
Rev.1.00 Apr 10, 2006 page 2 of 7
Pin Arrangement
1
8
4
3
2
MR
SWG
(Top view)
VDD18
CRext
6
7
5
VDD33
RESN
RESP
GND
Pin Description
Pin No.
1
Pin Name
VDD33
Function
Input power supply pin for 3.3-V voltage. Recommended operating range is 2.7 to 3.6 V.
Set the input voltage to 0.033 V/
μ
s or less when starting up.
Active-low reset signal output pin. By connecting to RESN pin, CMOS output can be used.
If using open-drain, please connect pull-down resistor.
Active-low reset signal output pin. By connecting to RESP pin, CMOS output can be used.
If using open-drain, please connect pull-up resistor.
GND pin
External PMOS gate control signal to be set between 1.8-V power supply and 1.8-V voltage
input of microcomputer.
Input power supply pin for 1.8-V voltage. Recommended operating range is 1.65 to 3.6 V.
Connecting pin for Rext resistance and Cext capacity that determine the delay time of reset
signal.
3.3 k
or more is recommended for resistance. The delay time, t
DLY
, is given by the
following formula.
t
DLY
= Cext
×
Rext [s]
2
RESP
3
RESN
4
5
GND
SWG
6
7
VDD18
CRext
8
MR
Pin to provide reset manually. MR pin is pulled-up to VDD33 through internal resistor.
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