參數(shù)資料
型號(hào)： RM5261A-350-H
廠商： PMC-SIERRA INC
元件分類： 微控制器/微處理器
英文描述： CONNECTOR ACCESSORY
中文描述： 64-BIT, 350 MHz, MICROPROCESSOR, PQFP208
封裝： HEAT SPREADER, MQFP-208
文件頁(yè)數(shù)： 16/42頁(yè)
文件大?。?/td> 683K
代理商： RM5261A-350-H
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
16
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
3.11 System Control Co-processor (CP0)
The system control coprocessor, also called coprocessor 0 or CP0 in the MIPS architecture, is
responsible for the virtual memory sub-system, the exception control system, and the diagnostics
capability of the processor. In the MIPS architecture, the system control co-processor (and thus the
kernel software) is implementation dependent.
The memory management unit controls the virtual memory system page mapping. It consists of an
instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint
instruction and data address translation buffer, JTLB, and co-processor registers used by the virtual
memory mapping sub-system.
3.12 System Control Co-Processor Registers
The RM5261A incorporates all system control co-processor (CP0) registers on-chip. These
registers provide the path through which the virtual memory system’s page mapping is examined
and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM5261A includes registers to
implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data
error detection.
Figure 4 shows the CP0 registers.
Figure 4 CP0 Registers
0
47
TLB
(entries protected
from TLBWR)
EntryHi
10*
EntryLo0
2*
EntryLo1
3*
PageMask
5*
Wired
6*
Random
1*
Index
0*
Status
12*
Cause
13*
EPC
14*
ErrorEPC
30*
Count
9*
Compare
11*
Context
4*
PRId
15*
Config
16*
TagHi
29*
TagLo
28*
ECC
26*
CacheErr
27*
BadVAddr
8*
LLAddr
17*
* Register number
XContext
20*
Used for memory
management
Used for exception
processing
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