參數(shù)資料
型號(hào)： RM5261A-300-HI
廠商： PMC-SIERRA INC
元件分類： 微控制器/微處理器
英文描述： CONNECTOR ACCESSORY
中文描述： 64-BIT, 300 MHz, MICROPROCESSOR, PQFP208
封裝： HEAT SPREADER, MQFP-208
文件頁(yè)數(shù)： 21/42頁(yè)
文件大小： 683K
代理商： RM5261A-300-HI
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
21
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
Table 3 Cache Attributes
Characteristics
Size
Organization
Line size
Index
3.20 Write buffer
Writes to external memory, whether cache miss write-backs or stores to uncached or write-through
addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data
pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in
parallel with the memory update. For uncached and write-through stores, the write buffer
significantly increases performance by decoupling the
SysAD
bus transfers from the instruction
execution stream.
3.21 System Interface
The system interface consists of a 64-bit Address/Data bus with 8 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring data between the processor and memory at a peak rate of 800MB/sec with a
100MHz SysClock.
Figure 6 shows a typical embedded system using the RM5261A. In this example, a bank of
DRAMs and a memory controller ASIC share the processor’s
SysAD
bus while the memory
controller provides separate ports to a boot ROM and an I/O system.
Instruction
32KB
2-way set associative
32B
vAddr
11..0
pAddr
31..12
n.a.
sub-block
sequential
entire line
per-word
set A
Data
32KB
2-way set associative
32B
vAddr
11..0
pAddr
31..12
write-back/write-through
sub-block
sequential
first double
per-byte
set A
Tag
Write policy
Read order
Write order
miss restart after transfer of
Parity
Cache locking
相關(guān)PDF資料
PDF描述
RM5261A-350-H CONNECTOR ACCESSORY
RM5261 RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
RM5261-200-Q RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
RM5261-200-QI RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
RM5261-250-Q RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RM5261A-300HI-B002 制造商:PMC Sierra from Components Direct 功能描述:MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHNOLOGY - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261A-300HI-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin MQFP
RM5261A-300J-B002 制造商:PMC Sierra from Components Direct 功能描述:RM5261A-300J-B002, MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHN - Trays 制造商:PMC SIERRA 功能描述:PMC SIERRA RM5261A-300J-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin LFMQFP
RM5270-150S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5270-200S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5271-200S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*