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參數(shù)資料
| 型號： | RM5261-200-QI |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| 中文描述： | 64-BIT, 200 MHz, MICROPROCESSOR, PQFP208 |
| 封裝： | POWER, QFP-208 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 683K |
| 代理商： | RM5261-200-QI |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002241, Issue 1
9
RM5261
Microprocessor with 64-Bit System Bus Data Sheet
Released
1
Features
Dual Issue superscalar microprocessor
200, 250, 266 MHz operating frequencies
320 Dhrystone 2.1 MIPS
High-performance system interface
64-bit multiplexed system address/data bus for optimum price/performance
High-performance write protocols maximize uncached write bandwidth
Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
IEEE 1149.1 JTAG boundary scan
Integrated on-chip caches
32KB instruction and 32KB data
—
2 way set associative
Virtually indexed, physically tagged
Write-back and write-through on a per page basis
Pipeline restart on first doubleword for data cache misses
Integrated memory management unit
Fully associative joint TLB (shared by I and D translations)
48 dual entries map 96 pages
Variable page size (4 KB to 16 MB in 4x increments)
High-performance floating-point unit: up to 530 MFLOPS
Single cycle repeat rate for common single-precision operations and some double-pre-
cision operations
Two cycle repeat rate for double-precision multiply and double precision combined
multiply-add operations
Single cycle repeat rate for single-precision combined multiply-add operation
MIPS IV instruction set
Floating point multiply-add instruction increases performance in signal processing
and graphics applications
Conditional moves to reduce branch frequency
Index address modes (register + register)
Embedded application enhancements
Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply
instruction
I and D cache locking by set
Optional dedicated exception vector for interrupts
Fully static 0.25 micron CMOS design with power down logic
Standby reduced power mode with WAIT instruction
2.5 V core with 3.3 V IOs
208-pin PQFP package
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5261-250-Q | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM5261-266-Q | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| RM7065 | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| RM7065A | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7065A-300T | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5261-225Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261-250Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261-250Q-C001 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261-250Q-C001, MICROPROCESSOR 64-BIT 0.25 UM CMOS TECHNOL - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261-250Q-C001, Microprocessor 64-Bit 0.25 um CMOS Technology 3.3V 208-Pin PQFP |
| RM5261-266Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus |
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