參數(shù)資料
型號(hào): RM3183CH
元件分類: 接收器
英文描述: Line Receiver
中文描述: 線路接收器
文件頁數(shù): 35/45頁
文件大?。?/td> 287K
代理商: RM3183CH
RM3283
PRODUCT SPECIFICATION
2
Functional Description
The RM3283 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor input network, a window comparator, and a logic
output buffer stage. The first stage provides overvoltage
protection and biases the signal using voltage dividers and
current sources, providing excellent input common mode
rejection. The test inputs are provided to set the outputs to a
predetermined state for built-in channel test capability. If the
test inputs are not used, they should be grounded.
The window comparator section detects data from the resis-
tor input network. A Logic 1 corresponds to ARINC “High”
state (OUTA) and a Logic 0, to ARINC “Low” state (OutB).
An ARINC “Null” state at the inputs forces both outputs to
Logic 0. Threshold and hysteresis voltages are generated by
a bandgap voltage reference to maintain stable switching
characteristics over temperature and power supply
variations.
The output stage generates a TTL compatible logic output
capable of driving 3mA of load.
Pin Assignments
Absolute Maximum Ratings
Parameter
Supply Voltage (V
V
LOGIC
Voltage
Logic Input Voltage
Temperature Range
Min.
Max.
+36
+7
Units
V
V
V
C
C
C
C
C
CC
to V
EE
)
-0.3
-65
-55
-55
V
LOGIC
+150
+125
+175
+300
+260
+ 0.3
Storage
Operating
°
°
Junction Temperature
Lead Soldering Temperature
°
60 sec., DIP, LCC
10 sec., SOIC
°
°
20
2
3
4
5
6
7
8
9
10
-V
S
TestA
DIP and SOIC
Top View
Cap2B
In2B
Out2B
In2A
Cap2A
Out2A
+V
L
NC
11
12
13
14
15
16
17
18
19
TestB
+V
S
Out1B
NC
GND
Out1A
In1B
Cap1B
In1A
Cap1A
65-3283-02
65-3283-03
4
5
6
7
8
In2B
Out2B
In2A
Cap2A
Out2A
14
15
16
17
18
GND
Out1A
In1B
Cap1B
In1A
C
1
T
2
-
S
T
C
1
2
3
N
O
+
S
N
+
L
1
1
1
1
9
LCC
Top View
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