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參數(shù)資料
| 型號： | RM3182A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | ARINC 429 Differential Line Driver(ARINC 429標(biāo)準(zhǔn)差分線驅(qū)動器) |
| 中文描述： | ARINC公司429差分線路驅(qū)動器（個ARINC 429標(biāo)準(zhǔn)差分線驅(qū)動器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 66K |
| 代理商： | RM3182A |
PRODUCT SPECIFICATION
RM3182A
11
Mechanical Dimensions
(continued)
28-Terminal LCC
DETAIL "A"
B1
A1
A
D2
(j) x 45
L1
L2
DETAIL "A"
E
LID
See Note 1
Index Corner
D
(h) x 45
3 PLCS
4
B3
L3
PLANE 2
PLANE 1
A
A1
B1
B3
D/E
.060
.050
.022
.006
.442
.100
.088
.028
.022
.460
1.52
1.27
.56
.15
11.23
2.54
2.24
.71
.56
11.68
Symbol
Inches
Min.
Max.
Min.
Max.
Millimeters
Notes
D1/E1
D2/E2
e
h
j
L1
L2
L3
.050 BSC
.040 REF
.020 REF
.045
.075
1.27 BSC
1.02 REF
.51 REF
1.14
1.91
7
7
28
28
.300 BSC
.150 BSC
7.62 BSC
3.81 BSC
3, 6
3, 6
2
2, 5
4
4
5
ND/NE
N
.015
.38
.003
.08
.055
.095
1.40
2.41
Notes:
1.
The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown on
planes 1 and 2. Plane 1 terminal 1 identification may be an extension
of the length of the metallized terminal which shall not
be wider than
the B1 dimension.
Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.).
Dimension "A" controls the overall package thickness. The maximum
"A" dimension is the package height before being solder dipped.
The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three dimensional
space traversing all of the ceramic layers in which a castellation was
designed. Dimension "B3" maximum and "L3" maximum define the
maximum width and depth of the castellation at any point on its
surface. Measurement of these dimensions may be made prior to
solder dripping.
Chip carriers shall be constructed of a minimum of two ceramic layers.
2.
3.
4.
5.
6.
e
D1
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