參數(shù)資料
型號: RLD03N06CLE
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: JFETs
英文描述: 0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped Logic Level N-Channel Enhancement-Mode Power MOSFETs
中文描述: 60 V, 6 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-251AA
文件頁數(shù): 9/13頁
文件大?。?/td> 188K
代理商: RLD03N06CLE
9
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Temperature Compensated PSPICE Model for the RLD03N06CLE, RLD03N06CLESM,
RLP03N06CLE
SUBCKT RLD03N06CLE 2 1 3;
CA 12 8 0.547e-9
CB 15 14 0.547e-9
CIN 6 8 0.301e-9
rev 4/18/94
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 20 17 18 66.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 2.96e-9
LSOURCE 3 7 2.96e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
QCONTROL 20 70 7 QMOD 1
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 1.123
RGATE 9 20 3200
RIN 6 8 1e9
RSOURCE1 8 70 RDSMOD 1.12
RSOURCE2 70 7 RSMOD 2.16
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.22
.MODEL DBDMOD D (IS = 7.97e-17 RS = 1.82 TRS1 = 3.91e-3 TRS2 = 1.24e-5 CJO = 3.00e-10 TT = 1.83e-7)
.MODEL DBKMOD D (RS = 3150 TRS1 =0 TRS2 = 0)
.MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0)
.MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 74.2e-12 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 1.67 KP = 3.40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL QMOD NPN (BF =5)
.MODEL RBKMOD RES (TC1 = 4e-4 TC2 = 1.13e-8)
.MODEL RDSMOD RES (TC1 = 6.80e-3 TC2 = 6.5e-6)
.MODEL RSMOD RES (TC1 = 2.95e-3 TC2 = -1e-6)
.MODEL RVTOMOD RES (TC1 = -2.22e-3 TC2 = -1.95e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF = -1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF = -3)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.85 VOFF = 2.15)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.15 VOFF = -2.85)
.ENDS
NOTE:
1. For further discussion of the PSPICE model consult
A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records 1991.
1
GATE
LGATE
RGATE
EVTO
18
8
9
+
DESD1
DESD2
12
13
8
14
13
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
R
IN
C
IN
MOS1
MOS2
RDRAIN
DBREAK
EBREAK
DBODY
LDRAIN
DRAIN
RSOURCE2
LSOURCE
SOURCE
RBREAK
RVTO
VBAT
IT
VTO
ESG
DPLCAP
6
6
8
10
5
16
21
11
17
18
8
-
14
5
8
6
8
7
3
17
18
19
91
2
+
+
+
+
+
+
RSOURCE1
70
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