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參數(shù)資料
| 型號： | RDC-19220-202S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PDIP40 |
| 封裝： | 2 X 0.600 INCH, 0.200 INCH HEIGHT, PLASTIC, DDIP-40 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 256K |
| 代理商： | RDC-19220-202S |
5
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
The components of gain coefficient are error gradient, integrator
gain and VCO gain. These can be broken down as follows:
RV, RB, and CBW are selected by the user to set velocity scaling
and bandwidth.
GENERAL SETUP CONSIDERATIONS
DDC has external component selection software which consid-
ers all the criteria below, and in a simple fashion, asks the key
parameters (carrier frequency, resolution, bandwidth, and track-
ing rate) to derive the external component value.
The following recommendations should be considered when
installing the RDC-19220 Series R/D converters:
1) In setting the bandwidth (BW) and Tracking Rate (TR)
(selecting five external components), the system require-
ments need to be considered. For greatest noise immunity,
select the minimum BW and TR the system will allow.
2) Power supplies are ±5 V dc. For lowest noise performance
it is recommended that a 0.1 F or larger cap be connected
from each supply to ground near the converter package.
3) Resolver inputs and velocity output are referenced to A
GND. This pin should be connected to GND near the con-
verter package. Digital currents flowing through ground will
not disturb the analog signals.
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod
with 2 Vrms input)
- Integrator Gain =
volts per second per volt
- VCO Gain =
LSBs per second per volt
where: Cs = 10 pF
Fs = 67 kHz when Rs = 30 k
Fs = 100 kHz when Rs = 20 k
Fs = 134 kHz when Rs = 15 k
CVCO = 50 pF
Cs Fs
1.1 CBW
1
1.25 RV CVCO
ERROR PROCESSOR
RESOLVER
INPUT
(
θ)
VELOCITY
OUT
DIGITAL
POSITION
OUT (
φ)
VCO
CT
S
A
+ 1
1
B
S
+ 1
10B
H = 1
+
-
e
A2
S
-12
db/oct
BA
2A
-6 db/oct
10B
ω (rad/sec)
2A
2 2 A
ω (rad/sec)
f
= BW (Hz) =
BW
2 A
π
CLOSED LOOP
(B = A/2)
GAIN = 0.4
GAIN = 4
(CRITICALLY DAMPED)
OPEN LOOP
FIGURE 3. TRANSFER FUNCTION
BLOCK DIAGRAM #2
FIGURE 4. BODE PLOTS
4) The BIT output which is active low is activated by an error
of approximately 100 LSBs. During normal operation for step
inputs or on power up, a large error can exist.
5) This device has several high impedance amplifier inputs
(+C, -C, +S, -S, -VCO and -VSUM). These nodes are sensi-
tive to noise and coupling components should be connected
as close as possible.
6) Setup of bandwidth and velocity scaling for the optimized
critically damped case should proceed as follows:
Note: DDC has software available to perform the previous calcu-
lations. Contact DDC to request software or visit our web-
site at www.ddc-web.com to download software.
- Select the desired f BW (closed loop) based on overall
system dynamics.
- Select f carrier ≥ 3.5f BW
- Compute Rv = 55 k
x
- Compute CBW (pF) =
- Where Fs = 67 kHz for R CLK = 30 K
100 kHz for R CLK = 20 K
134 kHz for R CLK = 15 K
- Compute RB =
- Compute
3.2 x Fs (Hz) x 108
Rv x (f BW)2
For the converter’s max tracking rate value,
see the row indicated in TABLE 4.
Application max. rate
0.9
CBW x f BW
CBW
10
{
}
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