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參數(shù)資料
| 型號： | RDC-19220-113Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDIP40 |
| 封裝： | CERAMIC, DDIP-40 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 304K |
| 代理商： | RDC-19220-113Q |
16
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
N-09/03-0
LOS will be detected if both sin and cos input voltages are less
than 800 mV peak.
ENCODER EMULATION
The RDC-19220 can be made to emulate incremental optical
encoder output signals, where such an interface is desired. This
FIGURE 16B. FILTERED/BUFFERED ENCODER EMULATOR CIRCUIT
LSB +1
LSB
EL
-5 V
CB (ZI)
(ZI)
A
B
FIGURE 16A. INCREMENTAL ENCODER EMULATION
maintain the loop at a null. BIT will also be set low for a detected
total Loss-of-Signal (LOS). The BIT signal may pulse during cer-
tain error conditions (i.e., converter spin around or signal ampli-
tude on threshold of LOS).
LSB +1
LSB
EL
-5 V
RDC-19220
CB/NRP
R1
2k
D1
1N4148
C1
220 pF
4
5
C2
220 pF
13
12
C3
120 pF
9
10
R2
2k
U2A
74AC86
2
1
A
B
NRP
8
6
11
3
NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL
COMPATIBLE LOGIC WILL SKEW THE DELAYS.
U2D
74AC86
U2B
74AC86
U2C
74AC86
R3
2k
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