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參數(shù)資料
| 型號(hào)： | RD-19240FSA00T |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | RD-19240FSA00T |
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6
Data Device Corporation
www.ddc-web.com
RD-19240
Pre 1-1-04/05-0
5) Setup of bandwidth and velocity scaling for the optimized crit-
ically damped case should proceed as follows:
As an example:
Calculate component values for a 16-bit converter with 100Hz
bandwidth, a tracking rate of 10 RPS and a full scale velocity
of 4 Volts.
Note: Software that will automatically calculate the data in step 5 is available on
our web site at www.ddc-web.com.
6) Selecting a fBW that is too low relative to the maximum appli-
cation tracking rate can create a spin-around condition in
which the converter never settles. The relationship to insure
against spin-around is as follows (TABLE 2.):
- Rv =
= 97655
- Compute CBW (pF) =
= 21955 pF
- Compute RB =
= 410 k
4 V
10 rps x 216 x 50 pF x 1.25 V
0.9
21955 x 10 -12 x 100 Hz
3.2 x 67 kHz x 108
97655 x 100 Hz2
- Select the desired f BW (closed loop) based on overall
system dynamics.
- Select f carrier
≥ 3.5f BW
- Select the applications tracking rate (in accordance with TABLE 3),
and use appropriate values for R SET and R CLK
- Compute Rv =
- Compute CBW (pF) =
- Where Fs = 67 kHz for R CLK = 30 K
100 kHz for R CLK = 20 K
125 kHz for R CLK = 15 K
- Compute RB =
- Compute
3.2 x Fs (Hz) x 108
Rv x (f BW)2
Full Scale Velocity Voltage
Tracking Rate (rps) x 2 resolution x 50 pF x 1.25 V
0.9
CBW x f BW
CBW
10
When using the built-in -5 V inverter, the maximum tracking rate
should be scaled for a velocity output of 3.5 V max. Use the fol-
lowing equation to determine tracking rate used in the formula in
Step 5:
Note: When using the highest BW and Tracking Rates, use of the -5 V inverter is
not recommended.
HIGHER TRACKING RATES AND
CARRIER FREQUENCIES
Maximum tracking rate is limited by the velocity voltage satura-
tion (nominally 4 V) and the maximum internal clock rate (nomi-
nally 1,333,333 Hz for R CLK = 30k). To achieve higher tracking
rates, a higher internal counting rate must be programmed by
setting RCLK to a value less than 30k. See TABLE 4 for the
appropriate values.
Select freq/resolution from TABLE 4 then reference TABLE 3 for
max tracking rate. The Rv resistor and an internal 50pF capacitor
are configured as an integrating circuit that resets to zero after a
count occurs in either direction. This circuit acts as a VCO with
velocity as its input and CB as its output. The Rv resistor and an
internal 50pF capacitor determine the maximum rate of the VCO.
Rv must be chosen such that the maximum rate of the VCO is
less than the maximum internal clock rate. Choose the tracking
rate in accordance with TABLE 3 to insure this relationship. The
rates shown in TABLE 3 are based on ~90% of the nominal inter-
nal clock rate.
The relationship between the velocity voltage and the VCO rate
is given by:
Note: RC “Rcurrent” = RSET
RS “Rsample” = RCLK
Velocity Voltage
VCO Frequency
1
(Rv x 50 pF x 1.25)
=
TR (required) x (4.0) = Tracking rate used in calculation
(3.5)
TABLE 2. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW
RESOLUTION
1
10
0.50
12
0.25
14
7) When using the built-in -5 V inverter (connect as shown) the cur-
rent drain from the +5 V supply doubles. No external -5 V sup-
ply is needed. The power supply 47f caps shown may be sub-
stituted with 10f caps if the P/S lines are clean (min noise).
When using a +5 V and -5 V supply to power the converter, pins
VSSP, NCAP, PCAP, and VDDP must be no connection.
FIGURE 5. -5V BUILT-IN INVERTER
+
10
F/10V
VDD
PCAP
+5V
NCAP
GND
AGND
VSSP
RD-19240
47
F/10V
VDD
VDDP
VSS*
VSS
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