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參數(shù)資料
| 型號(hào)： | RD-19240FSA00T |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁(yè)數(shù)： | 14/18頁(yè) |
| 文件大小： | 215K |
| 代理商： | RD-19240FSA00T |
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5
Data Device Corporation
www.ddc-web.com
RD-19240
Pre 1-1-04/05-0
reduce the gain and ripple at the carrier frequency and above.
The settings of the various error processor gains and break fre-
quencies are done with external resistors and capacitors so that
the converter loop dynamics can be easily controlled by the user.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and its Bode Plots
(open and closed loop). These are shown in FIGURES 2, 3, and 4.
The open loop transfer function is as follows:
where:
A is the gain coefficient
A2 = A
1A2
B is the frequency of lead compensation
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
where:
C
s = 10 pF
F
s = 70 kHz when Rs = 30 k
F
s = 100 kHz when Rs = 20 k
F
s = 125 kHz when Rs = 15 k
C
vco = 50 pF
R
V, RB, and CBW are selected by the user to set velocity scaling
and bandwidth.
- Error Gradient = 0.011 volts per LSB (CT+Error
Amp+Demod with 2 Vrms input)
- Integrator gain =
volts per second per volt
- VCO Gain =
LSBs per second per volt
1
1.25 R
vCvco
C
SFS
1.1C
BW
Open Loop Transfer Function =
A
(S
B
+ 1
)
2
S
( S
10B
+ 1
)
2
ERROR PROCESSOR
RESOLVER
INPUT
(
θ)
VELOCITY
OUT
DIGITAL
POSITION
OUT (
φ)
VCO
CT
S
A
+ 1
1
B
S
+ 1
10B
H = 1
+
-
e
A2
S
-12
db/oct
BA
2A
-6 db/oct
10B
ω (rad/sec)
2A
2 2 A
ω (rad/sec)
f
= BW (Hz) =
BW
2 A
π
CLOSED LOOP
(B = A/2)
GAIN = 0.4
GAIN = 4
(CRITICALLY DAMPED)
OPEN LOOP
FIGURE 3. TRANSFER FUNCTION BLOCK DIAGRAM #2
FIGURE 4. BODE PLOTS
GENERAL SETUP CONDITIONS
DDC has external component selection software that considers all
the criteria below and, in a simple fashion, asks the key parame-
ters (carrier frequency, resolution, bandwidth, and tracking rate) to
derive the external component values. For detailed setup informa-
tion refer to the RD/RDC Series Converters Applications Manual
(document #MN-19220XX-001) available at www.ddc-web.com.
The following recommendations should be considered when
installing the RD-19240 Resolver-to-Digital (R/D) converter:
1) When setting the bandwidth (BW) and Tracking Rate (TR)
(selecting five external components), the system require-
ments need to be considered. For the greatest noise immuni-
ty, select the minimum BW and TR the system will allow.
2) Power supplies are ±5 V DC. For lowest noise performance it
is recommended that a 0.1F or larger cap be connected from
each supply to ground near the converter package. When
using a +5 V and -5 V supply to power the converter, pads 22,
23, 25, and 26 must be no connection.
3) This converter has two internal ground planes, which reduce
noise to the analog input due to digital ground currents. The
resolver inputs and velocity output are referenced to AGND.
The digital outputs and inputs are referenced to GND. The
AGND and GND pads must be tied together as close to the
converter package as possible. Not shorting these pads
together as close to the converter package as possible will
cause unstable converter results.
4) The BIT output, which is active low, is activated by an error of
approximately 100 LSBs. During normal operation, for step
inputs or on power up, a large error can exist.
GAIN
11 mV/LSB
16 BIT
UP/DOWN
COUNTER
R1
VCO
RV
RB CBW
C
/10
BW
VEL
-VCO
H = 1
-VSUM
VEL
C F
S S
CT
+
-
RESOLVER
INPUT
(
θ)
RS
50 pf
CVCO
DIGITAL
OUTPUT
(
φ)
DEMOD
±1.25 V
THRESHOLD
1
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
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