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參數(shù)資料
| 型號： | R5F64342JFD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 18/110頁 |
| 文件大?。?/td> | 982K |
| 代理商： | R5F64342JFD |
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REJ03B0244-0030 Rev.0.30 Feb 14, 2008
Page 15 of 108
Under development
Preliminary Specification
Specifications in this preliminary version are subject to change.
R32C/134 Group
2. Central Processing Unit (CPU)
2.1
General Purpose Registers
2.1.1
Data Register (R2R0, R3R1, R6R4, and R7R5)
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.
Each of the registers can be divided into high-order and low-order 16-bit registers, e.g. R2R0 can be
divided into R2 and R0, R3R0 can be divided into R3 and R1, etc.
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: high-order (R2h,
and R3H), mid-high-order(R2L, and R3L), mid-low-order (R0H, and R1H), and low-order (R0L, and
R1L).
2.1.2
Address Register (A0, A1, A2, and A3)
These 32-bit registers have the similar functions to the data registers. They are also used for address
register indirect addressing and address register relative addressing.
2.1.3
Static Base Register (SB)
This 32-bit register is used for SB relative addressing.
2.1.4
Frame Base Register (FB)
This 32-bit register is used for FB relative addressing.
2.1.5
Program Counter (PC)
This 32-bit counter indicates the address of instruction to be executed next.
2.1.6
Interrupt Table Register (INTB)
This 32-bit register indicates the start address of a relocatable vector table.
2.1.7
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack
pointer (ISP). They are switched by the U flag. Refer to 2.1.8 “Flag Register (FLG)” for details on the
U flag.
The stack pointer (USP/ISP) to be used can be switched by the stack pointer select flag (U flag). This
flag is the bit 7 of the flag register (FLG).
A multiple of 4 should be set to USP or ISP, which enables faster interrupt sequence due to less mem-
ory access.
2.1.8
Flag Register (FLG)
This 32-bit register indicates the status of CPU.
2.1.8.1
Carry Flag (C flag)
This flag has a carry, borrow, or shifted-out bit etc. that has occurred in the arithmetic/logic unit.
2.1.8.2
Debug Flag (D flag)
This flag is exclusively used for debugger purpose. It should be written with 0.
2.1.8.3
Zero Flag (Z flag)
This flag becomes 1 when an operation results in 0; otherwise, it indicates 0.
2.1.8.4
Sign Flag (S flag)
This flag becomes 1 when an operation results in negative; otherwise, it indicates 0.
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