• 參數(shù)資料
    型號: R5F64179HDFD
    元件分類: 微控制器/微處理器
    英文描述: 64-BIT, FLASH, MICROCONTROLLER, PQFP144
    封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
    文件頁數(shù): 105/114頁
    文件大?。?/td> 851K
    代理商: R5F64179HDFD
    REJ03B0254-0110
    Rev.1.10
    Page 90 of 111
    Jun 23, 2010
    R32C/117 Group
    5. Electrical Characteristics
    VCC =5V
    Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta =Topr, unless otherwise noted)
    Note:
    1.
    The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
    respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
    calculation results in a negative value, modify the value to be set. For the details of how to set values,
    refer to the User’s manual.
    tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]
    tw(R) = Tw(R) × tc(Base) - 10 [ns]
    tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]
    tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]
    Table 5.35
    External Bus Timing (Separate bus)
    Symbol
    Characteristic
    Measurement
    condition
    Value
    Unit
    Min.
    Max.
    tsu(S-R)
    Chip-select setup time for read
    Refer to
    Figure 5.6
    (1)
    ns
    th(R-S)
    Chip-select hold time after read
    tc(Base) - 15
    ns
    tsu(A-R)
    Address setup time for read
    (1)
    ns
    th(R-A)
    Address hold time after read
    tc(Base) - 15
    ns
    tw(R)
    Read pulse width
    (1)
    ns
    tsu(S-W)
    Chip-select setup time for write
    (1)
    ns
    th(W-S)
    Chip-select hold time after write
    1.5 × tc(Base) - 15
    ns
    tsu(A-W)
    Address setup time for write
    (1)
    ns
    th(W-A)
    Address hold time after write
    1.5 × tc(Base) - 15
    ns
    tw(W)
    Write pulse width
    (1)
    ns
    tsu(D-W)
    Data setup time for write
    (1)
    ns
    th(W-D)
    Data hold time after write
    0ns
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