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參數(shù)資料
| 型號： | R5F6411FNFN |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 7/107頁 |
| 文件大?。?/td> | 1192K |
| 代理商： | R5F6411FNFN |
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A- 3
8
Completed “under development” phase of part numbers
R5F64110DFB, R5F64111DFB, R5F64112DFB, R5F64114DFB,
R5F64115DFB, and R5F64116DFB in Table 1.7
Added product information for 100-pin LGA and 80-/64-pin packages
to Table 1.7
9
Added product information for 100-pin LGA and 80-/64-pin packages,
and 32-Kbyte RAM to Figure 1.1
Deleted hyphenation for part number in Figure 1.1
11, 12,
14, 18,
21
Added Figures 1.3, 1.4, and 1.6 to 1.8 to provide block diagrams and
pin assignment for 100-pin LGA and 80-/64-pin packages
13
Changed the order of Notes in Figures 1.5
15-17
Added pin No. for 100-pin LGA package to Tables 1.8 to 1.10
19, 20,
22, 23
Added Tables 1.11 to 1.14 to provide pin characteristics for 80-/64-pin
packages.
24
Changed the following expression: “A ceramic resonator or a crystal
oscillator” for “Main clock input/output” in Table 1.15, to “A crystal, or a
ceramic resonator”
25
Modified descriptions for
HLDA and RDY of “Bus control pins” in Table
1.16
26
Changed the following expression: “selected” for “Input port” in Table
1.17
, to “selectable”
Modified description “TXD2” for TXD0 to TXD8 of “Serial interface” in
Table 1.17
, to “TXD2 output”
28-30
Added Tables 1.19 to 1.21 to provide pin definitions and functions for
80-/64-pin packages
Chapter 2. CPU
—
Made major text modifications to this chapter
33
Changed the following expression: “a requested interrupt’s priority
level” in line 2 of 2.1.8.11, to “the interrupt request level”
Chapter 3. Memory
35
Made major text modifications to this chapter
Changed RAM size “40” in line 7 of this chapter, to “63”, and address
“0000A3FFh” in line 8, to “0000FFFFh”
Added descriptions for 32-Kbyte RAM and 128-Kbyte ROM to Figure
3.1
Changed two “can be”s in Notes 3 and 4 of Figure 3.1, to “becomes”s
Chapter 4. SFRs
36
Changed hexadecimal format of reset values for registers CCR and
FMCR in Table 4.1, to binary
Added FEBC3 register to addresses 000010h-000011h in Table 4.1
Changed FEBC register for addresses 00001Ch-00001Dh, to FEBC0
in Table 4.1
Modified the following register name in Table 4.1: “Chip-select
Boundary (between n and n + 1) Setting Register”, to “Chip-select n
and n + 1 Boundary Setting Register”
REVISION HISTORY
R32C/111 Group Datasheet
Rev.
Date
Description
Page
Summary
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| R5F64111NFB | 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP100 |
| R5F64115DFB | 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP100 |
| R5F64111DFB | 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP100 |
| R5F6411FNFP | 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP80 |
| R5F64111NFB | 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F6411FNFN#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 5.5V 512K ROM - Trays |
| R5F6411FNFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6411FNFP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 5.5V 512K ROM - Trays |
| R5F6411FNLG | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F6411FNLG#U0 | 功能描述:MCU 256+8KB FLASH 100-TFLGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:M16C/R32C/100/111 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標(biāo)準(zhǔn)包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設(shè)備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲器容量:384KB（384K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b，D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 產(chǎn)品目錄頁面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
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