參數(shù)資料
型號: R5F6411FDFN
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 28/107頁
文件大?。?/td> 1192K
代理商: R5F6411FDFN
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 25 of 99
R32C/111 Group
1. Overview
Table 1.16
Pin Definitions and Functions for the 100-pin Package (2/4)
Bus control pins
A0/D0 to A7/D7
I/O
VCC2
Output of address bits (A0 to A7) and input/output
of data (D0 to D7) by time-division while accessing
an external memory space with multiplexed bus
A8/D8 to
A15/D15
I/O
VCC2
Output of address bits (A8 to A15) and input/
output of data (D8 to D15) by time-division while
accessing an external memory space with 16-bit
multiplexed bus
BC0/D0
I/O
VCC2
Output of byte control (
BC0) and input/output of
data (D0) by time-division while accessing an
external memory space with multiplexed bus
CS0 to CS3
O
VCC2
Chip select output
WR0/WR1/WR/
BC0/BC1/RD
O
VCC2
Output of write, byte control, and read signals.
Either
WRx or WR and BCx can be selected by a
program.
Data is read when
RD is low.
When
WR0, WR1, and RD are selected,
data is written to the following address:
an even address, when
WR0 is low
an odd address, when
WR1 is low
on 16-bit external data bus
When
WR, BC0, BC1, and RD are selected,
data is written, when
WR is low
and
the following address is accessed:
an even address, when
BC0 is low
an odd address, when
BC1 is low
on 16-bit external data bus
ALE
O
VCC2
Latch enable signal in multiplexed bus format
HOLD
I
VCC2
The MCU is in a hold state while this pin is held
low
HLDA
O
VCC2
This pin is driven low while the MCU is held in a
hold state
RDY
I
VCC2
Bus cycle is extended by the CPU if this pin is low
on the falling edge of the BCLK
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