參數(shù)資料
型號(hào)： R5F6411FDFN
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 101/107頁(yè)
文件大?。?/td> 1192K
代理商： R5F6411FDFN
REJ03B0227-0110 Rev.1.10 Sep 17, 2009
Page 91 of 99
R32C/111 Group
5. Electrical Characteristics
VCC1 =VCC2 =3.3 V
Switching Characteristics (VCC1 =VCC2 =3.0 to 3.6V, VSS =0V, and Ta =Topr, unless otherwise noted)
Note:
1.
The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and
respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the
calculation results in a negative value, modify the value to be set. For the details of how to set values,
refer to the Hardware manual.
tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]
tw(R) = Tw(R) × tc(Base) - 10 [ns]
tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]
tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]
Table 5.57
External Bus Timing (Separate bus)
Symbol
Characteristic
Measurement
condition
Value
Unit
Min.
Max.
tsu(S-R)
Chip-select setup time for read
Refer to
Figure 5.6
(1)
ns
th(R-S)
Chip-select hold time after read
tc(Base) - 10
ns
tsu(A-R)
Address setup time for read
(1)
ns
th(R-A)
Address hold time after read
tc(Base) - 10
ns
tw(R)
Read pulse width
(1)
ns
tsu(S-W)
Chip-select setup time for write
(1)
ns
th(W-S)
Chip-select hold time after write
1.5 × tc(Base) - 10
ns
tsu(A-W)
Address setup time for write
(1)
ns
th(W-A)
Address hold time after write
1.5 × tc(Base) - 10
ns
tw(W)
Write pulse width
(1)
ns
tsu(D-W)
Data setup time for write
(1)
ns
th(W-D)
Data hold time after write
0ns
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