
Rev. 1.00 Sep. 13, 2007 Page xv of xxviii
9.3.6
DMA Mode Control Register (DMDR)............................................................ 275
9.3.7
DMA Address Control Register (DACR) ......................................................... 284
9.3.8
DMA Module Request Select Register (DMRSR) ........................................... 290
9.4
Transfer Modes ................................................................................................................. 290
9.5
Operations......................................................................................................................... 291
9.5.1
Address Modes ................................................................................................. 291
9.5.2
Transfer Modes ................................................................................................. 295
9.5.3
Activation Sources ............................................................................................ 300
9.5.4
Bus Access Modes ............................................................................................ 302
9.5.5
Extended Repeat Area Function ....................................................................... 304
9.5.6
Address Update Function using Offset ............................................................. 307
9.5.7
Register during DMA Transfer ......................................................................... 311
9.5.8
Priority of Channels .......................................................................................... 316
9.5.9
DMA Basic Bus Cycle...................................................................................... 318
9.5.10
Bus Cycles in Dual Address Mode ................................................................... 319
9.5.11
Bus Cycles in Single Address Mode................................................................. 328
9.6
DMA Transfer End ........................................................................................................... 333
9.7
Relationship among DMAC and Other Bus Masters ........................................................ 336
9.7.1
CPU Priority Control Function Over DMAC ................................................... 336
9.7.2
Bus Arbitration among DMAC and Other Bus Masters ................................... 337
9.8
Interrupt Sources...............................................................................................................338
9.9
Usage Notes ...................................................................................................................... 341
Section 10 Data Transfer Controller (DTC) ........................................................343
10.1
Features............................................................................................................................. 343
10.2
Register Descriptions ........................................................................................................ 345
10.2.1
DTC Mode Register A (MRA) ......................................................................... 346
10.2.2
DTC Mode Register B (MRB).......................................................................... 347
10.2.3
DTC Source Address Register (SAR)............................................................... 348
10.2.4
DTC Destination Address Register (DAR)....................................................... 349
10.2.5
DTC Transfer Count Register A (CRA) ........................................................... 349
10.2.6
DTC Transfer Count Register B (CRB)............................................................ 350
10.2.7
DTC enable registers A to H (DTCERA to DTCERH) .................................... 350
10.2.8
DTC Control Register (DTCCR) ...................................................................... 351
10.2.9
DTC Vector Base Register (DTCVBR)............................................................ 353
10.3
Activation Sources............................................................................................................ 353
10.4
Location of Transfer Information and DTC Vector Table ................................................ 353
10.5
Operation .......................................................................................................................... 358
10.5.1
Bus Cycle Division ........................................................................................... 360
10.5.2
Transfer Information Read Skip Function ........................................................ 362